L13 – VHDL Language Elements

VHDL Language Elements  Elements needed for FPGA design Types  Basic Types  Resolved Types – special attributes of resolved types Concurrent Statements Sequential Statements Design Units Packages  Ref: text Unit 10, 17, 20 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU2

VHDL Data Types  VHDL Data Types Numerous – comparable to modern high level languages The ones useful for synthesis will be highlighted  Predefined Type BIT  A predefined type with values of ‘0’ and ‘1’  Declaration – TYPE BIT IS (‘0’,’1’); 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU3

Type BIT  Type BIT A predefined type with values of ‘0’ and ‘1’ Declaration – TYPE BIT IS (‘0’,‘1’); An enumeration type – a list of possible values. The elements of the list are in single ‘s’ if a single element. If more than 1 character then no ‘s’. Also predefined – TYPE BOOLEAN IS (FALSE, TRUE) 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU4

Enumeration Types  Predefined TYPEs BIT and BOOLEAN  Enumeration types initialize to the leftmost element of the set for signals and variables declared to be of the type.  Other Examples – User defined TYPE opcode IS (op0,op1,opOR,opAND, opNOT, opXOR,opXNOR,opADD,opSUB, opINC,opDEC);  Usage SIGNAL instr : opcode; VARIABLE mybit : BIT; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU5

Other types  Integer TYPE INTEGER – range is at least 32 bit 2’s complement  Character TYPE CHARACTER – single ASCII characters  Real numbers TYPE REAL – floating point type – IEEE standard 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU6

Physical Types  Predefined TYPE time IS RANGE 0 to 1E18  UNITS FS; -- femtosecond PS = 1000 FS; -- picosecond NS = 1000 PS; -- nanosecond US = 1000 NS; -- microsecond MS = 1000 US; --millisecond SEC = 1000 MS; -- second MIN = 60 SEC; -- minute  END UNITS; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU7

Physical Types  User defined TYPE distance IS RANGE 0 TO 1E16  UNITS A; -- angstrom, base unit NM = 10A; -- nanometer MIL = A; -- mil INCH = 1000 mil; -- inch  END UNITS; USAGE  VARIABLE X : distance; VARIABLE Y : time;  X := 5 A + 14 inch – 45 mil;  Y := 3 ns + 5 min; NOTE: Any implementation allows for declaration of physical types with a range of to /2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU8

Subtypes  SUBTYPES SUBTYPE POS_INT IS RANGE 1 TO integer’high; VARIABLE mri : POS_INT; “A subtype of type is also of the type”.  NOTE : VHDL CODE IS CASE INSENSITIVE!! Subtype pos_int IS RANGE 1 to INTEGER’High; is the same as the declaration above 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU9

Composite types  ARRAYS TYPE my_word IS ARRAY (0 to 31) of BIT; TYPE regs IS ARRAY (7 downto 0) of my_word;  Unconstrained ARRAYS TYPE memory IS ARRAY (INTEGER range <>) of my-word; USE:  VARIABLE my_mem : MEMORY (0 to 65536); 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU10

Predefined Arrays  SUBTYPE positive IS INTEGER range 1 to ITEGER’HIGH; INTEGER’HIGH is the largest integer for this installation  TYPE string IS ARRAY (POSITIVE RANGE <>) of CHARACTER;  SUBTYPE natural IS INTEGER range 0 to ITEGER’HIGH;  TYPE bit_vector IS ARRAY (NATURAL range <>) of BIT; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU11

Some examples  EXAMPLES of use VARIABLE message : STRING(1 to 17) := “THIS is a message”; Text inside a string is case sensitive message (1 to 16) := “Modified Message”;  WHAT WOULD BE CONTAINED IN THE VARIABLE MESSAGE???? SIGNAL low_byte : BIT_VECTOR (0 to 7); SIGNAL fword : BIT_VECTOR (15 downto 0); 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU12

Other types  Composite types – RECORDS  Dynamic records – ACCESS TYPES  File I/O – FILE TYPES 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU13

Declarations  SIGNALS For use in entities, architectures, procedures, functions, and process. Scope depends upon where declared – can be sort of global (scope of architecture) Have a value and time component Assignments do-not take place immediately – assignment of new values are scheduled Delaration in Entities, Architectures, Concurrent Procedures  SIGNAL my_sig : BIT :=‘1’;  SIGNAL my_int : INTEGER := 45; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU14

Declarations  VARIABLES For use in processes, procedures and functions Scope limited to the process, procedure, or function in which declared. Cannot be declared in the declarative region of architectures!!!! Have no time component Any assignment takes place immediately upon assignment.  VARIABLE my_var : BIT; Sometimes used in synthesis 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU15

Declarations  ALIASES SIGNAL real_num : BIT_VECTOR (0 TO 31); ALIAS sign : BIT is real_num(0); ALIAS exp : BIT_VECTOR(0 TO 7) is real_num (1 TO 8); ALIAS fract : BIT_VECTOR (0 to 23) is real_num (9 TO 31);  Then in the design you can assign or use any of the names real_num, sign, exp, fract. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU16

Declarations  CONSTANTS CONSTANT pi : REAL := ; CONSTANT cycle_time : TIME := 75 ns; Can be declared and used but cannot be assigned to  COMPONENT Declaration needed for hierarchical models COMPONENT local_component_name  PORT(port declarations from component’s entity) END COMPONENT; The easy way to do a component declaration is to copy the ENTITY Declaration, change ENTITY TO COMPONENT, delete the IS and change END xxx to END COMPONENT Once declared, the COMPONENT must be configured 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU17

Operations  LOGICAL OPERATORS:: AND | OR | NAND | NOR | XOR | XNOR | NOT  APPLY TO TYPES BIT AND BOOLEAN  RELATIONAL OPERATORS:: = | /= | | >=  Result of comparison with relational operators is BOOLEAN  ADDING OPERATORS:: + | - | &  + and - work with REAL and INTEGER types  & is the concatenation operator and works with types BIT and BIT_VECTOR  Result of & is concatenation of left + right X <= “000”; Y <= “1111”; Z <= X & Y would now have value “ ” scheduled for assignment 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU18

Concatenation example VARIABLE r,x : BIT_VECTOR (31 downto 0); VARIABLE y : BIT_VECTOR (0 to 31); SIGNAL s, pval : BIT: SIGNAL Q76 : BIT_VECTOR( );  Using part of a vector is termed slicing R(15 downto 0) := x(31 downto 24) & y(0 to 7); r(31 downto 30) := s & pval; Q76 <= r & s & pval; How large does Q76 have to be? 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU19

Size of Q76?  The size of the concatenated vector MUST match the size of the target.  Q76 Could be 0 to 33 OR 33 downto 0; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU20

More operators  SIGN:: + | -  MULTIPLYING:: * | / | MOD | REM * and / can be used for integer and real MOD and REM are valid only for type integer  MISCELANOUS:: ** | ABS | NOT 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU21

Concurrent statements  Concurrent statements are those that can appear between the BEGIN and END of an architecture.  With these statements you model the component or system to be modeled.  These statements have semantic meaning and execute independent of the order in which they appear in the model.  These statements – Boolean equations – synthesize well. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU22

Component Instantiation  A concurrent statement and how ‘structural’ architectures are created. Synthesize well.  Component Instantiation Statement Prior to use the component must be declared and configured in the declarative region of the architecture. LABEL : component_name  [generic_map_aspect]  [port_map_aspect] FOR all : component_name USE ENTITY work.component_name(arch_name); 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU23

Example of use  Consider that the following is already analyzed and in your library ENTITY wigit IS  PORT(p1, p2 : IN BIT); END wigit; ARCHITECTURE Y OF wigit IS …..; ARCHITECTURE Z OF wigit IS …..; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU24

Declaration of component  ARCHITECTURE use_it OF xyz IS COMPONENT wigit  PORT(p1, p2 : IN BIT); END COMPONENT: -- and the configuration is FOR C0 : wigit USE ENTITY work.wigit(y); FOR OTHERS : wigit USE ENTITY work.wigit(Z);  Note that the component declaration is the same as the ENTITY declaration except that ENTITY becomes COMPONENT and it is END COMPONENT 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU25

The instantiation SIGNAL A,B,C,D : BIT;  BEGIN CO : wigit PORT MAP (A, B); C1 : wigit PORT MAP (p1 =>C, p2=>D); 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU26

What about repetitive structures?  When you have repetitive structures to build up with instantiations  GENERATE STATEMENT – automates the instantiation of repetitive structures 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU27

 ENTITY bit_comparator IS PORT(a,b,gt,eq,lt : IN bit; a_gt_b, a_eq_b,a_lt_b : OUT bit);  END bit_comparator;  ARCHITECTURE bit_comp_arch OF bit_comparator IS  BEGIN  a_gt_b b) OR ((a=b) AND gt) ELSE ‘0’;  a_eq_b <= ‘1’ WHEN ((a=b) AND eq) ELSE ‘0’;  a_lt_b <= ‘1’ WHEN ((a<b) OR ((a=b) AND lt) ELSE ‘0’;  END bit_comp_arch; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU28

The multi-bit comparator  ENTITY byte_comparator IS PORT (a,b : IN bit_vector (7 downto 0); --a & b data gt,eq,lt: IN bit; --previous slice results a_gt_b, a_eq_b, a_lt_b : OUT bit); --outputs END byte_comparator;  Now we will look at three possible approaches to implementing this.  The first is of course 8 component instantiations 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU29

Start of ARCHITECTURE  ARCHITECTURE iterative OF byte_comparator IS --do component declaration and configuration COMPONENT bit_comparator  PORT (a,b,gt,eq,lt:IN bit;a_gt_b, a_eq_b, a_lt_b:OUT bit); END COMPONENT; FOR ALL: bit_comparator USE ENTITY WORK.bit_comparator(bit_comp_arch); --internal signal to connect bit positions SIGNAL igt,ieq,ilt : bit_vector (0 to 6); 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU30

8 Component instantiations  BEGIN C0 : bit_comparator PORT MAP (a(0),b(0),gt,eq,lt,igt(0),ieq(0),ilt(0)); C1 : bit_comparator PORT MAP (a(1),b(1),igt(0),ieq(0),ilt(0),igt(1),ieq(1),ilt(1)); C2 : bit_comparator PORT MAP (a(2),b(2),igt(1),ieq(1),ilt(1),igt(2),ieq(2),ilt(2)); C3 : bit_comparator PORT MAP (a(3),b(3),igt(2),ieq(2),ilt(2),igt(3),ieq(3),ilt(3)); C4 : bit_comparator PORT MAP (a(4),b(4),igt(3),ieq(3),ilt(3),igt(4),ieq(4),ilt(4)); C5 : bit_comparator PORT MAP (a(5),b(5),igt(4),ieq(4),ilt(4),igt(5),ieq(5),ilt(5)); C6 : bit_comparator PORT MAP (a(6),b(6),igt(5),ieq(5),ilt(5),igt(6),ieq(6),ilt(6)); C7 : bit_comparator PORT MAP (a(7),b(7),igt(6),ieq(6),ilt(6),a_gt_b,a_eq_b, a_lt_b);  END; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU31

Generate version1  Use component instantiations to handle boundries  BEGIN --start with lsb where lsb is rightmost bit C0: bit_comparator PORT MAP(a(0),b(0),gt,eq,lt,igt(0),ieq(0),ilt(0)); C1to6: FOR i IN 1 to 6 GENERATE  C: bit_comparator PORT MAP (a(i),b(i),igt(i-1),ieq(i-1),ilt(i-1), igt(i),ieq(i),ilt(i)); END GENERATE; --end with msb where msb is leftmost bit C7: bit_comparator PORT MAP (a(7),b(7),igt(6),ieq(6),ilt(6),a_gt_b,a_eq_b,a_lt_b);  END iterative; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU32

Generate Version 2 - Nested  BEGIN C_all: FOR i IN 0 to 7 GENERATE --handle lsb where lsb is rightmost bit lsb: IF i=0 GENERATE  least : bit_comparator PORT MAP (a(i),b(i),gt,eq,lt, igt(0),ieq(0),ilt(0)); END GENERATE; --handle msb where msb is leftmost bit msb: IF i=7 GENERATE  most : bit_comparator PORT MAP (a(i),b(i),igt(i-1),ieq(i-1),ilt(i-1), a_gt_b,a_eq_b,a_lt_b); END GENERATE; --handle remaining bit slices mid: IF i>0 AND i<7 GENERATE  rest: bit_comparator PORT MAP (a(i),b(i),igt(i-1), ieq(i-1), ilt(i-1), igt(i),ieq(i),ilt(i)); END GENERATE;  END iterative; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU33

Lecture summary  VHDL Data Types  VHDL concurrent language statements  VHDL generate  VHDL concurrent statements synthesize well. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU34