CPLD Vs. FPGA Positioning Presentation

Agenda Architecture Descriptions Gate Counting Common Terms CPLD FPGA Advantages / Disadvantages Gate Counting Common Terms Positioning

Basic Definitions CPLD FPGA Course Grained Architecture Best for Wide, Fast Function Processing Relatively Small Designs FPGA Fine Grained Architecture Best for Narrow / Pipelined Functions Large Designs LUT 4

FPGA Architecture FPGA CPLD Global Routing Pool (GRP) Boundary Scan Interface GOE0 GOE1 SET/RESET TDI TCK TMS TDO CLK 1 CLK 0 1 CLK 3 CLK 2 VCCIO Input Bus Generic Logic Block I/O 0 / TOE I/O 1 I/O 2 I/O 3 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 44 I/O 45 I/O 46 I/O 47 I/O 48 I/O 49 I/O 50 I/O 51 I/O 68 I/O 69 I/O 70 I/O 71 I/O 72 I/O 73 I/O 74 I/O 75 I/O 92 I/O 93 I/O 94 I/O 95 I/O 96 I/O 97 I/O 98 I/O 99 I/O 116 I/O 117 I/O 118 I/O 119 I/O 120 I/O 121 I/O 122 I/O 123 I/O 140 I/O 141 I/O 142 I/O 143 I/O 167 I/O 166 I/O 165 I/O 164 I/O 147 I/O 146 I/O 145 I/O 144 I/O 191 I/O 190 I/O 189 I/O 188 I/O 171 I/O 170 I/O 169 I/O 168 I/O 215 I/O 214 I/O 213 I/O 212 I/O 195 I/O 194 I/O 193 I/O 192 I/O 239 I/O 238 I/O 237 I/O 236 I/O 219 I/O 218 I/O 217 I/O 216 I/O 263 I/O 262 I/O 261 I/O 260 I/O 243 I/O 242 I/O 241 I/O 240 I/O 287 I/O 286 I/O 285 I/O 284 I/O 267 I/O 266 I/O 265 I/O 264 FPGA CPLD

High Density Logic Overview FPGA HDPLD or CPLD A B C Field Programmable Gate Arrays Small Logic Building Blocks Register Intensive Distributed Interconnect Slower pin to pin performance, due to lots of routing, but pipelining can help Good at “Narrow Gating” Funcitions Datapath Random Logic High-Density or Complex PLDs Large Logic Building Blocks PLD-Like Architectures Centralized Interconnect Fast Predictable Performance Good at “Wide Gating” Functions State Machines Counters FPGAs and CPLDs Can Compliment One Another In the Same Design!

Performance FPGA - 4 input Look Up Table (LUT) CPLDs have wide fan in Two possible implementations Pipelining (preferred) High internal frequency achievable higher latency Two levels of logic Lower latency, but high frequencies not achievable CPLDs have wide fan in Single level allows high frequency AND low latency Very small functions burn logic LUT 4 LE LUT 4 Interconnect Local Row Logic 68 Macrocell

Predictability and Delay Row / column design of FPGA Design changes potentially changes routing Routing changes result in timing changes Larger delta in I/O to I/O delay Design for worst case delay Centralized routing of CPLDs Consistent Routing through GRP All GRP lines equally loaded Re-route has minimal effect on timing Wide inputs results in fewer paths Higher speed Better predictability

FPGA Architecture FPGAs use fine grain logic blocks Many of these logic blocks are used to implement logic functions due to fine grain blocks, 16 LBs for 16-Bit adder FPGAs Work Best With One - hot encoding for state functions Fine Grain / Abundance of Registers makes One-Hot a good fit Register Logic

FPGA EPROM Most FPGAs are volatile SRAM Devices are reprogrammed on power-up Program can be stored in companion, EPROM next to FPGAs Device can be programmed with P via Flash programming Logic is not available when power is initially applied FPGA EPROM or P

FPGA Vs CPLD Logic Element FPGA Has a Basic, Fine Grain Logic Element Typical FPGA has 4 Inputs and 8 Product Terms Per Logic Element Wide Designs Speed Limitation Can be Overcome with Pipelining CPLD Has Complex Logic Element 5KVG Family has 68 Inputs and 32 Product Terms Per Logic Element The CPLD Has Less Registers but uses these registers more efficiently Simple Designs Use up the Registers and Logic Elements are Under Utilized CPLD vs FPGA Input Ratio = 17 : 1 CPLD vs FPGA Product Term Ratio = 4 : 1 Logic Element 8 PTs FPGA 4 1 Logic Element 32 PTs CPLD 68 1

Technology Comparisons Feature E2CMOS Flash SRAM Antifuse Reprogrammability Yes Yes Yes NO In-System Programmable Yes Yes Yes NO (Volatile) Program Time Fast Med. Fast Slow Erase Time Fast Slow Fast N/A (OTP) Testability Full Full Full Limited External Hardware No No EPROM Pgmr

Gate Counting

CPLD Vs. FPGA Fitting Number of PLD Gates or Registers Doesn’t Tell the Entire Story, The Application Does Even among equivalent product types, Gate count is “specsmanship”, the only real way to see if a design will fit or fit better is to run it! Applications Needing High Speed and Predictability Should Use CPLD Large Register Intensive Logic Applications Should Use FPGA Most Designs Have a Mixture of Qualities that Could Fit Either, So Both CPLD and FPGA Should Be Considered

A Gate Is a Gate Is a Gate FPGA and CPLD Both Build Gates Out of Transistors The Basic CMOS Gates Are the Same in Both Architectures Inverter NAND NOR Example NAND B A F VCC B A F

CPLD Gate Count Vs FPGA Gate Count It is Difficult to Compare Apples to Apples What Is an “Equivalent PLD Gate”? A Simple PLD Gate Is Considered 2-input AND How Many Simple PLD Gates to Build an 8-input AND? Seven FPGA Vendors Have Different Standards for Gate Counts A Higher Percentage of Gates Are Used for Interconnect in FPGA and some Vendors count Memory in Total Gate Count The First Order of Importance Is to Have Enough Registers to Compete, Not Fight Over Gate Counts The Only Way To Know if a Design Fits is to FIT IT!!!

Terms

FPGA Terms FPGA - Field Programmable Gate Array SRAM - Static RAM Program stored in outside EPROM, intelligent controller or through JTAG Port, FPGAs must be reprogrammed on every power-up Configuration EPROM External hardware used to hold FPGA programming file ICR - In-Circuit Reconfigurability Anti-fuse - One-Time Programmable (OTP) (Quicklogic and Actel) Interconnect - Basic Routing element FPGAs rely on a Fine Grain routing structure LUT - Look-Up Table 4-input SRAM based look-up table produces the output of any 4 input function LE/CLB - Logic Element Smallest logic unit. 4 input Look-Up Table, Carry/cascade chains, register and register control signals

FPGA Terms LAB - Logic Array Block (Altera) Consists of 8 LEs and associated control signals and routing EAB - Embedded Array Block (Altera) High level building block, includes Ram and registers One Hot Encoding When single registers (bits) are used to represent states instead of the common binary method Example: 20 state-state machine One Hot: 20 registers (bits) Binary: 5 registers (bits) Pipeline Putting functions in an “assembly line” format. Small portions done quickly allows a high clock speed and results at short intervals. The drawback is results take longer to get from input to output (latency) Register Register Register Register No Clk Delay 1 Clk Delay 2 Clk Delay 3 Clk Delay

FPGA Terms SoC MPI EBR PLC PIO CIB PFU SLIC System on a Chip Microprocessor Interface EBR Embedded Block RAM PLC Programmable Logic Cell PIO Programmable Input/Output Cells CIB Common Interface Block PFU Programmable Function Unit SLIC Decoder / PAL like logic

Positioning

CPLDProduct Positioning FPGA/FPSC FPGA/FPSC ASIC Mach ASSP ROM Chip Set Memory GDX 5K Micro- Processor 5K GDX SPEED DENSITY

CPLD Product Positioning FPGA / FPSC Data Path Logic consolidation DSP Functions 5KVG Wide Decode Buss Control (16-32-64 bit Buses) In One Level Complex High Speed Control Fast Muxing Density Mach/Mach4K High Speed Decode Small High speed Control ASIC Fixes PCI Arbitration Speed

CPU Requirements Density Propagation Delay Datapath FPSCs Datapath Large FPGAs Fast Control / Datapath Density 5K Family M4K Family Wide Datapath Switching Fast address decode and Control logic Bus Arbitration Small CPU Fast Slow Propagation Delay

Some CPLDs Can Do Large Designs 5KVG Mach4K FPGA CPLD Some Small Designs Fit Better in Large CPLDs, Some Designs Require FPGA features

Summary Understand the Design CPLDs Are Best Suited for: Don’t Assume the Best Hardware is an FPGA or CPLD CPLDs Are Best Suited for: Wide Designs Speed Critical, Low Latency, Low Skew Relatively Small Hot-Plugable FPGAs Are Best Suited for: Large Register Intensive Designs Narrow Gating, Pipeline-able Fit the Design to Determine the Size in Our Devices