Integrated VLSI Systems EEN4196 Title: 4-bit Parallel Full Adder

 Introduction  Design Methodology  Schematic Diagram  Simulated Result  Layout  Conclusion

4-bit Parallel Full Adder

4-bit Parallel Full Adder Binary Addition and Operation

In our full adder design, we are using the 0.35 µm CMOS technology. So the length of the transistor we fixed to 0.35 µm. L = 0.35 µm The default ratio of W to L W/L = 3 So, we design the width of the NMOS 2.5 times its length WN = 0.35 µm x 3 = 1.05 µm As the width of the PMOS is 2 times the width of NMOS, hence WP = 1.05 µm x 2 = 2.1 µm

Schematic Diagram of Full Adder

Schematic Diagram of 4-bit Parallel Full Adder

 Output for First Block

 Output for Second Block

 Output for Third Block

 Output for Fourth Block

Power Dissipation As temperature increases, power dissipation increases Temperature, o CPower Dissipation, W m m m

 Propagation Delay  Proportional  As the temperature increases, the propagation delay increases  Due to degradation of carrier mobilities when the temperature is increased. Temperature (°C) Rising edge delay (ps) Falling edge delay (ps)

Layout of One Full-Adder Block

 Same transistor types are grouped together  less complex design.  To reduce the total size occupied.  reduce power consumption.  The rule of thumb technique  reduce the collision between metal routings and to reduce the complexity during top-level design.

 Transistor count: 112 (28 per full adder circuit)  Layout area: 163.4µm x 227.1µm  Power dissipation (27 o C): mW

 In conclusion, the schematic designed in this project is acceptable, at which the performance and delay is under reasonable range. The design can be considered as successful, due to the adequate precision and low power consumption. Future improvement on the current design is possible to achieve higher performance.