A Low-Power Precomputation-Based Parallel CAM Chi-Sheng Lin, Jui-Chang, Bin-Da Liu IEEE2003.

Slides:

Advertisements

Similar presentations

Transmission Gate Based Circuits

Advertisements

CSET 4650 Field Programmable Logic Devices

Figure (a) 8 * 8 array (b) 16 * 8 array.

Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course MOS circuits: basic construction.

Introduction to Digital Systems By Dr. John Abraham UT-Panam.

1 A New Successive Approximation Architecture for Low-Power Low-Cost A/D Converter IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.38, NO.1, JANUARY 2003 Chi-sheng.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN1600) Lecture 21: Dynamic Combinational Circuit Design Prof. Sherief Reda Division of.

Chapter 09 Advanced Techniques in CMOS Logic Circuits

ECE 424 – Introduction to VLSI Design Emre Yengel Department of Electrical and Communication Engineering Fall 2014.

Introduction to CMOS VLSI Design Lecture 18: Design for Low Power David Harris Harvey Mudd College Spring 2004.

Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE VLSI Circuit Design Lecture 9 - Combinational.

Overview Memory definitions Random Access Memory (RAM)

Introduction to CMOS VLSI Design CAMs, ROMs, and PLAs

EE40 Lec 20 MOS Circuits Reading: Chap. 12 of Hambley

Die-Hard SRAM Design Using Per-Column Timing Tracking

Low-Power CMOS SRAM By: Tony Lugo Nhan Tran Adviser: Dr. David Parent.

S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 20: Combinational Circuit Design (2/3) Prof. Sherief Reda Division of Engineering,

On-Line Adjustable Buffering for Runtime Power Reduction Andrew B. Kahng Ψ Sherief Reda † Puneet Sharma Ψ Ψ University of California, San Diego † Brown.

Lecture 19, Slide 1EECS40, Fall 2004Prof. White Lecture #19 ANNOUNCEMENTS Midterm 2 Thursday Nov. 18, 12:40-2:00 pm A-L initials in F295 Haas Business.

Introduction to CMOS VLSI Design Circuit Families.

Circuit Families Adopted from David Harris of Harvey Mudd College.

Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Topics n Memories: –ROM; –SRAM; –DRAM. n PLAs.

Digital CMOS Logic Circuits

Lecture 21, Slide 1EECS40, Fall 2004Prof. White Lecture #21 OUTLINE –Sequential logic circuits –Fan-out –Propagation delay –CMOS power consumption Reading:

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 18: Static Combinational Circuit Design (2/2) Prof. Sherief Reda Division.

Digital Integrated Circuits for Communication

1 EE 587 SoC Design & Test Partha Pande School of EECS Washington State University

MOS Transistors The gate material of Metal Oxide Semiconductor Field Effect Transistors was original made of metal hence the name. Present day devices’

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. C H A P T E R 14 Advanced MOS and Bipolar Logic Circuits.

EKT 221 : Digital 2 Memory Basics

EE 447 VLSI Design Lecture 8: Circuit Families.

A Low-Power CAM Design for LZ Data Compression Kun-Jin Lin and Cheng-Wen Wu, IEEE Trans. On computers, Vol. 49, No. 10, Oct Presenter: Ming-Hsien.

Washington State University

CMOS DYNAMIC LOGIC DESIGN

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Topics n Latches and flip-flops. n RAMs and ROMs.

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Topics Memories: –ROM; –SRAM; –DRAM; –Flash. Image sensors. FPGAs. PLAs.

Ratioed Circuits Ratioed circuits use weak pull-up and stronger pull-down networks. The input capacitance is reduced and hence logical effort. Correct.

Microelectronic Circuits - Fourth Edition Sedra/Smith 0 PowerPoint Overheads to Accompany Sedra/Smith Microelectronic Circuits 4/e ©1999 Oxford University.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 3: September 3, 2014 Gates from Transistors.

DCSL & LVDCSL: A High Fan-in, High Performance Differential Current Switch Logic Families Dinesh Somasekhaar, Kaushik Roy Presented by Hazem Awad.

1 Memory Hierarchy The main memory occupies a central position by being able to communicate directly with the CPU and with auxiliary memory devices through.

Digital Logic Design Instructor: Kasım Sinan YILDIRIM

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Topics n Pseudo-nMOS gates. n DCVS gates. n Domino gates.

A Robust Pulse-triggered Flip-Flop and Enhanced Scan Cell Design

Chapter 1 Combinational CMOS Logic Circuits Lecture # 4 Pass Transistors and Transmission Gates.

1/14 Synthesis and Design of Parameter Extractors for Low-Power Pre-computation-Based Content-addressable Memory Using Gate- Block Selection Algorithm.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Topics n Pseudo-nMOS gates. n DCVS logic. n Domino gates. n Design-for-yield. n Gates as IP.

Lecture 10: Circuit Families. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 10: Circuit Families2 Outline  Pseudo-nMOS Logic  Dynamic Logic  Pass Transistor.

Advanced VLSI Design Unit 04: Combinational and Sequential Circuits.

Introduction to CMOS VLSI Design Lecture 9: Circuit Families

Design and Analysis of A Novel 8T SRAM Cell December 14, 2010 Department of Microelectronic Engineering & Centre for Efficiency Oriented Languages University.

MEMORY ORGANIZATION - Memory hierarchy - Main memory - Auxiliary memory - Cache memory.

11. 9/15 2 Figure A 2 M+N -bit memory chip organized as an array of 2 M rows  2 N columns. Memory SRAM organization organized as an array of 2.

Dynamic Logic Dynamic Circuits will be introduced and their performance in terms of power, area, delay, energy and AT2 will be reviewed. We will review.

Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course MOS circuits: basic construction.

Other Logic Implementations

EE210 Digital Electronics Class Lecture 10 April 08, 2009

Memory Devices 1. Memory concepts 2. RAMs 3. ROMs 4. Memory expansion & address decoding applications 5. Magnetic and Optical Storage.

Solid-State Devices & Circuits

Seok-jae, Lee VLSI Signal Processing Lab. Korea University

1 Recap: Lecture 4 Logic Implementation Styles:  Static CMOS logic  Dynamic logic, or “domino” logic  Transmission gates, or “pass-transistor” logic.

1 Clockless Logic Montek Singh Thu, Mar 2, Review: Logic Gate Families  Static CMOS logic  Dynamic logic, or “domino” logic  Transmission gates,

Full Custom Associative Memory Core

Reading: Hambley Ch. 7; Rabaey et al. Sec. 5.2

Lecture 10: Circuit Families

Day 21: October 29, 2010 Registers Dynamic Logic

Jason Klaus, Duncan Elliott Confidential

AKT211 – CAO 07 – Computer Memory

Lecture 10: Circuit Families

Presentation transcript:

A Low-Power Precomputation-Based Parallel CAM Chi-Sheng Lin, Jui-Chang, Bin-Da Liu IEEE2003

Outline Intro CAM Design concept of PB-CAM Circuit Design of PB-CAM Improved PB-CAM Experimental Results Conclusion Conclusion

Intro Parallel CAM function is used widely lookup tables, databases, associative computing, data compression, etc. It need large power to achieve parallel CAM

CAM

Design concept of PB-CAM To reduce the comparison between input and the stored data. Add parameter extractor, parameter memory.

Design concept of PB-CAM

With an m words by n bits CAM size PB-CAM: 1th comparison: m*upon[log(n+2)] 2th comparison: (m*n)/(n+1) Total=1th+2th CAM: Total=M*(upon[log(n+2)+1])

Design concept of PB-CAM

Circuit Design of PB-CAM Traditional dynamic CAM: 1) The dynamic circuit needs an extra precharge time for each data searching operation. 2) The dynamic circuit has some problems, such as charge sharing and noise problems. 3) A clock signal is necessary to handle the circuit operation. 4) The noise margin of dynamic circuit is less than.

Traditional dynamic CAM

Circuit Design of PB-CAM static pseudo-nMOS circuit a) In the data searching operation, if the valid bit is invalid(v=1), then the PM1 is turned off and the NM1 is turned on. b) Otherwise, PM1 is turned on, and NM1 is turned off.

pseudo-nMOS circuit

Circuit Design of PB-CAM Another problem of pseudo-nMOS circuit.  power dissipation With an m-words CAM size input data only matches one stored data per data searching operation. m-1 data mismatching between stored data and input data per data searching operation.

Circuit Design of PB-CAM

parameter comparison circuit is used to control the pull-up PM1. Therefore, the number of PB-CAM word circuits that consume static power is reduced to ((m/n-1)-1).

Circuit Design of PB-CAM Traditional CAM cell is constructed by typical nine-transistor six-transistor SRAM cell to store a data bit, an XOR-type comparison circuit containing two nMOS transistors, and an nMOS pull-down device to drive the word match line

Circuit Design of PB-CAM

Proposed PB-CAM cell five-transistor D-latch device to store a data bit and a NAND-type comparison circuit containing two nMOS transistors to drive the word match line. To achieve low-voltage operation, the feedback inverter (INV2) is a weak-driving design to allow the input data(BL) to be stored in the D- latch device easily.

Circuit Design of PB-CAM

Advantage: 1. Searching time is better 2. Simplifies HW design 3. reduces operating voltage Disadvantage 1. Access performance is poorer

Improved PB-CAM Because of the parameter extraction function lot difference between probability of parameters.

Table of 14 bits ones-count parameter extractor

Block XOR approach

Table of 14 bits Block XOR PB- CAM

Experimental Results

Conclusion Based on the precomputation methodology, the circuit reduces most of the comparison operations and transistors to achieve low-power, low-cost, and low- voltage features.