1 ALU ports can get input from any of the two registers ALU can perform one of the eight operations Shift unit can perform one of the four possible types of shifts Operations on data path Mem Unit Mem Addr WM EM Reg File Reg Addr WRER ALUALU 4-bit Reg 4-bit Reg MUXMUX MUXMUX LD1 M2 M1 LD2 OpCode Input enable M- Reg enable LDM ShiftShift

2 ALU operations are –000Output A100A + B –001Output B101A - B –010Output A and B –011Output A or B Shift Operation –00Shift left without M10Shift left with M –01shift right without M11Shift left with M On the main bus, we can enable output of ALU, M-register, Input, Register File, and Memory unit (only one of them at a time) The main bus data data can be written into the two registers, Register File, and Memory unit ALU output can also be written into M register ALU operations and data transfers

3 To transfer Input to any register –Enable input to main bus –Write in register by enabling LD1 or LD2 –Other control signals should be asserted in such a way so that they do not cause any change in state To transfer a register data to M register –Select register through one of the multiplexers –Select ALU operation to transfer selected port to output –Write in M register by asserting LDM signal To transfer Register file or memory unit output to a register –Select appropriate register in Register file or memory location in memory and enable appropriate unit output to bus –Write in a register using LD1 or LD2 Some actual transfers

4 We can eliminate some components in the data path For example two registers and multiplexers may not be needed The register file is two ported Modified Data Path Mem Unit Mem Addr WM EM ALUALU OpCode Input EI Reg File WA WR RA2RA1 EALU M- Reg EMR LDM SHIFTSHIFT Shift code

5 Register file contain R registers –R can be 4 or 8 or 16 or 32 Each register has n bits (n can be 4, 8, 16, or 32) n defines the data path width Register file has two R-to-1 n-bit multiplexers Each multiplexer multiplexes all register to select one to output Any register can be read out on any of the two ports –Each multiplexer needs a log R bits address (RA1 or RA2) Any register can be written using data on the bus –Write address is specified by WA (log R bits) –Write is enabled by WR signal Register File

6 An instruction specifies is a set of bit specifying an operation It includes –an operation code to specify an ALU function –RA1 and RA2 bits to specify two registers –WA to specify which register to write back –shift code to specify shift operation Includes operation like no shift, shift left or right with M register –Memory address and control to read or write memory Not every instruction specifies all instructions A nano instruction is set of control bits for all units Operations