October 10, 20001

2 USB 2.0 Compliance Program Overview Dan Froelich Intel

October 10, Agenda w USB-IF Compliance Testing History w Goals of the USB 2.0 Compliance Program w USB 2.0 Differences from USB 1.1 w New/Modified Compliance Tests – Electricals – USBCheck – Transaction Translator – System/Platform w High Speed Signal Quality Test Demonstration

October 10, History w USB-IF 1.1 Compliance Program – Long evolution from 1996 (USB 1.0) to today (2000) S3 Inrush Signal Quality, S1 USBCheck, Hidview, Interoperability Chap 11, OHCI, Current Chap 9, UHCI, Drop/Droop S3 Inrush Signal Quality, S1 USBCheck, Hidview, Interoperability Chap 11, OHCI, Current Chap 9, UHCI, Drop/Droop ‘96 Year TestingTesting TestingTesting LevelLevel LevelLevel ‘97 ‘98 ‘99 ‘00 ‘01

October 10, Compliance Program Evolution w The USB 2.0 Compliance Program is an extension of the USB 1.1 Compliance Program – Years of experience – Tools already in place USB 2.0 Compliance Program Will Start at a High Level! Today Tomorrow USB2.0 USB1.1

October 10, Goals of the Compliance Program w High Quality USB 2.0 Products w Stable, Repeatable, Well Documented Tests – Documented Test Procedures – Documented Test Assertions and Descriptions w Instantly Available Testing (Qualified Test Houses) w Leverage USB 1.1 Compliance Program – Reuse USB Check – Reuse Interoperability Test Procedures – Reuse Full and Low Speed Electrical Testing w Minimize Test Equipment Costs

October 10, Compliance Program Milestones w HS Testing Preview at October PlugFest – HS Signal Quality and TDR – USBCheck – TT Functional Testing w Logo Testing Availability – Schedule Testing at Intel Peripheral Integration Lab u Starting in November u Contact Dan Froelich, – Available at Plugfests in January – All Test HW and SW Available by Q3 2000

October 10, USB 1.1 Testing Modifications and Reuse w Power Measurements w USBCheck – Chapter 9 Additions – Chapter 11 Additions w Interoperability – HS Device and Hub Additions w USB 1.1 Test Fixtures – Droop/Drop – Inrush – FS/LS Signal Quality

October 10, USBCheck – Chapter 9 Additions w Other Speed Device Qualifier and Configuration Descriptors – HS/FS Devices Must Use In Either Environment – Standard Configuration Descriptors Only For Current Environment w Endpoint Packet Size and Interval Rules w Electrical Test Mode Support w HS Devices Tested At High and Full Speeds HS Capable Devices Must Function in FS Environments

October 10, Compliance Tool USBCheck

October 10, USBCheck – Chapter 11 Additions w TT Request Codes w Port Indicators w New Status Bits Windows 2000 Version of USBCheck Available Soon

October 10, Interoperability Testing w Same Tree For HS/FS/LS Testing w Similar To 1.1 Interopability – All Transfer Types – 5 hubs deep with 5 meter cables (i.e. Tier 6) – Mix of speeds w Test devices at both Full and High Speeds Root HS Hub DUT HS Hub Other Devices Other Devices FS Hub HS Hub

October 10, Existing – Test Fixtures w Current w Inrush w Drop w Droop w Full/Low Speed Signal Quality

October 10, What Changed For USB 2.0 w HS Electrical Signaling and Electrical Test Modes – Defined Receiver Characteristics – Repeatable Signal Quality Testing w Hub Transaction Translator for FS/LS Support w Other Speed Device Descriptors w Model Largely Unchanged – Device Framework – Power Management and Distribution – Cables, Connectors, and Topology

October 10, New Testing Areas w Electricals – High Speed Signal Quality – Time Domain Reflectometry (TDR) – Receiver Sensitivity and Squelch w Platform Testing – Electricals – Port Routing w More Extensive Hub Testing – High Speed Repeater – Transaction Translator

October 10, USB 2.0 Electrical Test Modes w High-speed Capable Devices/Hubs Must Support Test Modes w Test modes Enable Repeatable Testing w SetFeature(TEST_MODE) and SetPortFeature(PORT_TEST) Requests Provide Standard Means of Entering Mode w Exit Action is also Standardized – Upstream Facing Port – Power Cycle – Downstream Facing Port – Hub Reset

October 10, Test Points w Transmitter w Receiver (New) USB Cable Device Circuit Board Hub / Motherboard BConnectorAConnector TracesTraces Transceiver TransceiverTP4TP3TP2TP1

October 10, Usb 2.0 Test Fixture HS Relay Test Port InitializationPort Diff Probe DataGenerator 90 Ohms PowerSelectionCktPowerSelectionCkt Vbus1Vbus2 Vcc Gnd New Test Fixtures w Device and Host Tests – Signal Quality – TDR – Receiver Sensitivity – Chirp – J and K Levels

October 10, High Speed Signal Quality w USB 2.0 Spec Defines Required Eye Patterns – 6 Patterns u 4 correspond to external connectors (TP2 & TP3) u 2 correspond to internal connectors (TP1 & TP4) – Rise / Fall Times – Allowance for Jitter – Overshoot / Undershoot w Testing at External Connectors – New Test Fixture for HS Signal Quality Available Soon

October 10, HS Signal Quality Test Procedure w Put Device in Test Mode Test_Packet w Flip Test Fixture Relays To Route Output to 90 Ohm Termination w Capture Waveform w Analyze Data 90  Test Mode SWOscilloscope USB 2.0 Test Fixture HS Relay Differential Probe Device Under Test Test

October 10, HS Receiver Sensitivity and Squelch Test Procedure w DUT Placed In Test_SEO_NAK Mode w Data Generator Generates IN Packets w Device Must Respond For In Spec Packets w Device Must Not Respond to Out of Spec Data Generator Output Data Generator Test Mode SW USB 2.0 Test Fixture HS Relay Device Under Test Test Device Under Test Test SMA

October 10, Time Domain Reflectometer (TDR) w Means of Measuring a Receiver’s Impedance – Receiver idle: D+, D- both at 0 volts (Test Mode SE0_NAK) w Requires New Test Fixture w To be run on All Devices, Hubs, and Platforms ConnectorReferenceTime

October 10, TDR Test Procedure w Device Under Test Placed In Test_SEO_NAK Mode w Relay Switches Idle Data Lines to TDR w TDR Broadcasts Test Signal w TDR Measures Signal Reflections To Determine Termination And PCB Impedance TDR Test Mode SW USB 2.0 Test Fixture HS Relay Device Under Test Test Device Under Test Test SMA

October 10, Host turns on HS termination Reset CHIRP Test Procedure w CHIRP Testing – Measured with single ended probes – At the A-connector (TP2) w Important Parameters – Reset duration – CHIRP K amplitude – CHIRP K duration – HS termination timing – Host CHIRP amplitude

October 10, Platform Testing w Eye Pattern Testing at TP2 – Template 1 (Transmit) – Template 4 (Receive) w TDR Testing w Port Routing Motherboard A Connector Transceiver TP2 TP1 PC Platform Traces Platform Design Guide Available on USB.ORG Attend Platform Design Considerations Presentation

October 10, Port Routing Logic Ensure HS, FS, and LS Devices Recognized Correctly Companion USB 1.1 HC X Port Register High Speed HC TransceiverTransceiver Port Routing Logic Port Owner Control HC Configured Port Register HS Device Device LSDeviceFSDevice

October 10, Extensive Hub Testing w Signal Quality – Eye Patterns – At TP3 (downstream) in addition to TP2 (upstream) – Both Transmitting (Template 1) and Receiving (Template 4) w Hub Specific Commands – Port Test Modes w TDR Testing – All connectors (upstream B, downstream A) w Transaction Translator w Electrical HS Repeater Testing

October 10, Transaction Translator w What is a Transaction Translator? – Component of the hub that handles data transfers to/from full and low speed downstream devices w When is it Used? – Active when hub is configured at high speed and full and/or low speed devices connected downstream u Buffers data transfers u Finite space u 2 kind of Buffers - Periodic and Non-Periodic u 1 TT per hub OR 1 TT per port

October 10, Transaction Translator Hub Components HS Device Device LSDevice Port MHz 12 MHz 1.5 MHz Port 2 Port N FSDevice HubRepeaterHubRepeater Routing Logic HubControllerHubController Hub State Machines Machines High speed connection TT 1 TT 2 TT N

October 10, Transaction Translator Testing w Devices & Hubs of Mixed Speeds Below Hub – Rigorous Functional Tests With FS/LS Devices u Proper Enumeration of Devices u Perform LoopBacks (All Transfer Types) Ô Stress Periodic and Non-Periodic Buffers (Multiple Endpoints) Ô Check for Isochrony Hiccups Ô Data Integrity – Specific Test Cases For Possible Device Behaviors u Timeout, Stall, Protocol Violations, ETC Separate Hub Testing Presentation with TT Focus

October 10, Oscilloscope Requirements w List of Required Scope / Probe Capabilities – 5 G Samples/sec (Per Channel) – 2 GHz bandwidth – Accuracy Requirements w Tested Scopes and Probes – Scope: TDS 694C – 10 GS/s, 3 GHz – Probe: P6217 Fet probe – 4 GHz, 0.4 pf typ – More Scopes and Probes to be added

October 10, Conclusions w Two significant Additions for USB2.0 Compliance – Electrical Testing u HS Signal Quality u TDR u Receiver Sensitivity u Squelch – Transaction Translator Testing w Well Documented Tests – Test Procedures – Test Specifications

October 10, Demo High Speed Signal Quality Using Test Mode Test_Packet

October 10, Questions?