Lecture 2: Computer Architecture: A Science ofTradeoffs.

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Presentation transcript:

Lecture 2: Computer Architecture: A Science ofTradeoffs

Outline The ISA The Microarchitecture The System level

The ISA (visible to the software) Dynamic/Static Interface What at compile time, what at run time Rich instruction set vs. simpler instruction set Fixed-length, Uniform Decode vs. … Condition codes vs. … Load/Store vs. … Help for the Programmer vs. help for the uarchitect Addressing modes Data types Unaligned accesses

The ISA (continued) Hardware interlocks vs. … VLIW vs. … 0,1,2,3 address machine Compatibility vs. a new ISA Precise exceptions vs. … Vectored interrupts vs Polling Address space (16-bit  32-bit  64-bit)

Two example ISAs LC-3b (from EE 360n) Load/store, 3-address machine Few opcodes, addressing modes, data types Fixed length, uniform decode x86 Not load/store, 2-address machine Variable length, decoding nightmare Prefixes Many opcodes, addressing modes, data types Dense encoding (comprehensive instructions) Mod/RM, SIB, addressing mode offset, literal operand Virtual memory PLUS segmentation Memory-mapped PLUS I/O instructions

The Microarchitecture (underneath the hood) CPI vs. cycle time (or, IPC vs. frequency) in-order vs. out-of-order execution Speculate vs. stand around and wait Issue-width ASIC vs. programmed control Use of chip real estate Better branch predictor Accelerators Microcode Pipeline depth Cache structures

Microarchitecture (continued) Fault tolerance Yesterday: Tandem (Two cores in lock step) Tomorrow: repeat to remove errors (or 2 cores lockstep) On-chip latency near neighbor communication Branch target buffer saves a bubble on a taken branch Partitioning – until when?

The System MP granularity (loosely coupled vs. tightly) Distributed shared memory versus centralized Interconnection structure Use of commodity vs tailored parts What do we integrate on chip Memory controller Analog devices