CP208 Digital Electronics Class Lecture 3 February 11, 2009

2 In Today’s Class We Will Continue to Discuss: Chapter 1: Introduction to Electronics Amplifiers( Cont …) 1.7 Logic Inverters But First … Home Work No. 1

HW #1 Problem (points ??) In above ADC, Input changes from 0 to V MAX. (a)Show that the LSB corresponds to a change of V MAX / (2 N – 1) and it is a resolution of the ADC. (b)Show that Max Quantization Error in conversion = 0.5 x V MAX / (2 N – 1) (c)If V MAX = 5 V, how many bits are needed for a resolution of 1 m V or better? Calculate the Actual resolution? What is Quantization error?

HW Problem Solution (a) For N bits, there are: 2 N Levels from 0 to V MAX, and 2 N – 1Discrete Steps from 0 to V MAX. And, the Step Size is: = (Total Length) / (Total # of Steps) = V MAX / (2 N – 1) When only (LSB) b 0 = 1, it will add a step V MAX / (2 N – 1) to Total. That is, the LSB Corresponds to change of V MAX / (2 N – 1). It is also the smallest value possible (Resolution) of the ADC. 0VV MAX V b0b0 b1b1 b2b2 b N – 1 … Step Level

HW Problem Solution (Cont …) (b) The Error is Maximum (Highest) when the Analog value Falls in Middle of the Discrete Step. And, the Middle of Step is: = (Step Length) / 2 OR 0.5 x (Step Length) Max Quantization Error = 0.5 x V MAX / (2 N – 1) 0V b0b0 b1b1 Middle of Step Error is Max

HW Problem Solution (Cont …) (C) Now, if V MAX = 5 V, For a Resolution = 1 m V or better: Number of bits, N = ??? Resolution = V MAX / (2 N – 1), Therefore, (5) / (2 N – 1) ≤ 1 m V  2 N – 1 ≥ 5 / (1x10 -3 )  2 N ≥ 5 x  2 N ≥ 5001 Taking Log on both Sides, we get N x Log (2) ≥ Log (5001)  N = Log (5001) / Log (2)  N ≥ N = 13 (But N =12 for little less resolution than 1 mV) Calculate the Actual resolution? Resolution = V MAX / (2 N – 1) = 5 / ( ) = 0.6 m V ( = 1.22 mV When N = 12) What is Quantization error? Error is ½ of the Resolution = 0.5 x 0.6 = 0.3 mV or = 0.61 mV When N = 12

1.4.9 Symbol Convention Instantaneous Quantities Lower Case Symbol with Uppercase Sub i A (t), v C (t) DC Quantities Upper Case Symbol Uppercase Sub I A, V C Sine Wave Signal Amplitude Uppercase Letter with Lowercase Sub I a, V c

1.4.9 Symbol Convention PS (dc) Voltages Uppercase V with Double- letter Uppercase Sub, V DD Similar notation for Current from PS Incremental Signal Quantities Lowercase Symbol with Lowercase Sub i a (t), v c (t)

1.4.6 Amp Power Supplies Power supplied to Load by Amp is Greater than Power Drawn from Input Signal To supply that extra power the Amp Need DC Power Supplies for their Operation In addition the DC PS supply power that might be Dissipated in Internal Amp Ckt

Power Deliverd to Amp P dc = V 1 I 1 + V 2 I 2 Amp Power-balance Eq. P dc + P I = P L + P dissipated

Amp Efficiency η ≡ (P L / P dc ) x 100 What about P I and P dissipated ?? Power Efficiency is Important Performance Parameter for Amps that Handle Large Amounts of Power … … and Such Power Amplifiers are Used as Output Amps of Stereo Systems

Simple Ckt Diagram – We shall adopt the convention illustrated and will not Explicitly show connections of Amp to DC PS

Example 1.1 (Page 17) Data Given; V1=V2= 10V I1 = I2 = 9.5 mA v I = 1 V, v O = 9V R L = 1kΩ i I = 0.1 mA Find: A v, A i, A p,P dc, P dissipated, η

1.4.7 Amp Saturation Practically Amp Transfer Characteristics Only Remain Linear for Limited Range of I/O Voltages Amp Operated from 2 PS the Output Voltage can not exceed specified positive limit and can not decrease below specified negative limit

An Amplifier Transfer Characteristic. v I Must be kept within Linear Range of Operation.

1.4.8 Nonlinear TC and Biasing Except from output Saturation Effect the Amp TC have been assumed linear In Practical Amps the TC may exhibit nonlinearities of various magnitudes Biasing is a Simple Technique to Obtain Linear Amplification From Amp Having Nonlinear TC

Considerable Nonlinear Amp TC. Amp is Biased to Obtain Linear Operation and the Signal Amplitude is Kept Small

Time-varying Signal to be Amplified is Superimposed on the DC Bias V I and Total Instantaneous Input v I (t) = V I + v i (t) –And v O (t) = V O + v o (t) –With v o (t) = A v v i (t) –Where A v = dv O / dv I | at Q is the Slope of Almost Linear Segment of TC This Way Linear Amplification is Achieved with a Limitation of Keeping Input Signal Sufficiently Small

Example 1.2 Example 1.2 Transfer Characteristic of Amplifier. Note That Amplifier is Inverting (Negative Gain) Example 1.2 (Page 21)

1.7 Digital Logic Inverters Logic Inverter is a Most Basic Element in Digital Ckt Design Plays a Role Parallel to the Amp in analog Ckt We will get Introduced to Logic Inverter in This Section

1.7.1 Function of the Inverters Logic Inverter INVERTS the Logic Value of its Input Signal That is for 0 input, out put will be 1, and vice versa In Voltage Level Terms When v I is Low (close to 0) the v O will be high V DD

1.7.2 The Voltage Transfer Characteristic VTC to Quantify Operation of Inverter Observe the TC of Amplifier in Ex 1.2 This Inverting Amp can be used as Inverter when we use its Extreme Regions of Operation – Opposite to Amp Dig App Make Use of Gross nonlinearity exhibited by VTC

VTC of an inverter. V OH Does Not Depend on Exact Value of v I as long as v I ≤ V IL. When v I > V IL Inverter in Amp mode or Transition Region. V IL is Max Value That v I Can Have While Being Interpreted by Inverter as Representing Logic 0. V OL Does Not Depend on Exact Value of v I as long as v I ≥ V IH. V IH is Min Value That v I Can Have While Being Interpreted by Inverter as Representing Logic 1.

1.7.3 Noise Margins Insensitivity of Inverter Output to Exact Value of v I within allowed regions is great advantage over analog ckts. To Quantify Insensitivity Consider One Inverter Driving Similar Inverter Noise Margin for High Input NM H = V OH – V IH Noise Margin for Low Input NM L = V IL - V OL

Four Parameters V OH,V IH,V IL, and V OL Define VTC of Inverter and Determine its Noise Margin, Which in Turn Measures its Ability to Tolerate Input Signal Variations V OL : Output Low Level V OH : Output High Level V IL : Max Input as Logic 0 V IH : Min Input as Logic 1 NM L : Noise Margin for Low Input = V IL - V OL NM H : Noise Margin for High Input = V OH – V IH

1.7.4 The Ideal VTC What Makes an Ideal VTC for Inverter? Ideal VTC Maximizes the Noise margins and Distributes Them Equally B/W the Low and High Regions V OH is at Max Possible Value V DD V OL is at Min possible Value 0 V

The Ideal VTC (Cont…) V IL and V IH are equal at Mid of ( V DD /2) Width of Transition Region (Imp for Amp) is Zero Steep Transition at Threshold Voltage ( V DD /2) – Gain infinite Noise Margins are Equal NM H = NM L = V DD /2 CMOS Inverter Has Close to Ideal VTC

1.7.5 Inverter Implementation Implemented using Transistors Operating as Voltage Controlled Switches

Transistor Switches are NOT Perfect Their OFF Resistance is High, But ON Resistance is not Zero and Some BJTs Exhibit Offset Voltage as well The Result is That When v I is High V OL Is not Ideally Zero

More Elaborate Implementation Exists Utilizing Pair of Complementary Switches (CMOS Based). When I/P Low, V OH = V DD, No Current Flows When I/P High, R on Connect Ground, V OL = 0

1.7.6 Power Dissipation Digital Systems use large number of Logic Gates Space and Economy Require as Few IC as Possible Hence, As Many Logic gates As Possible on IC Chip In Present VLSI 100K+ gates on IC To Keep Acceptable limit of Power Dissipation in Chip, Power Dissipation/Gate Must be Minimum Power Dissipation is Very Important Performance Measure of Logic Inverter

When v I Low no Power Dissipated In other State Dissipation is V 2 DD /R and is Substantial This Dissipation Occurs even When Inverter not Switching -- Static Power Dissipation

This Inverter Exhibit No Static Power Dissipation BUT …

There is Always A component of Power Dissipation Due to Capacitance Cap Exists between Output Node of Inverter and Ground Internal Cap of Switches Wires Connecting Output to Other Ckts have Cap Input Cap of Any CKt Driven by Inverter

When Inverter is Switching from One State to Another, Current must Flow thru Switches to Charge and Discharge the Load Capacitance The Current Give Rise to dissipation Called Dynamic Power Dissipation (Chap 4)

1.7.7 Propagation Delay Inverters are Characterized in Terms of The Time Delay Between Switching of v I (Low to High) and Corresponding Change Appearing at the Output 2 Reasons for Propagation Delay: –Transistors (Switches) Exhibit Finite (nonzero) Switching Time –The Cap needs to Charge/Discharge before Output Change To Analyze Inverter Switching Need to Understand Time Response of Single-Time-Constant Ckts (STC) [Appendix D.4.1]

Step Function Applied to an STC Network with Time Constant τ, Out put at any time: y(t) = Y ∞ - ( Y ∞ - Y 0+ )e -t/τ Y ∞ is final value where response is heading Y 0+ value of response immediately after t=0 Output at any time t is difference between final value and gap whose initial value is Y ∞ - Y 0+ and shrinking exponentially Y ∞ = S and Y 0+ = 0, Thus y (t) = S(1- e -t/τ )

Example 1.6 Consider the Inverter in Fig. with a C=10 pF connected between the output and ground. Let V DD =5V, R=1kΩ, R on =100Ω and V offset =0.1V. If at t=0, v I goes low and neglecting the delay time of the switch, that is, assuming that it opens Immediately, Find the time for the Output to Reach ½ (V OH + V OL ). The Time to this 50% point on the out put waveform is defined as the Low-to-High Propagation Delay, t PLH.

Example 1.6 Before t =0 v I is high, and v O = V OL = V offset + V in R on V in R on = (V DD – V offset )xR on /(R+R on ) V OL = (5 – 0.1)x0.1/(1.1) v O = V OL = 0.55 V

Example 1.6 At t=0 SW opens, V across Cap cannot change instantaneously.  at t=0+ O/P v O (t0+) = Cap charges thru R and O/P rises Exponentially to V DD.  v O (∞) = V DD. Using the Output Eqn of STC Network for Step-function as I/P: y(t) = Y ∞ - ( Y ∞ - Y 0+ )e -t/τ v O (t) = v O (∞) – [v(∞) - v O (t0+) ] e -t/τ

Using v O (∞) = 5 V and v O (0+) = 0.55V in v O (t) = v O (∞) – [v(∞) - v O (t0+) ]e -t/τ We get: v O (t) = 5 – (5 – 0.55) e -t/τ v O (t) = 5 – 4.45 e -t/τ _____ (1) τ = RC. To Find t PLH … when t= t PLH v O (t=t PLH ) = 0.5(5+0.55) = 2.78 Eq (1) becomes: 2.78 = 5 – 4.45 e -tPLH /RC  4.45 e -tPLH /RC = 5 – 2.78 = 2.23  e tPLH /RC = 4.45/2.23 = Taking ln on both sides: t PLH / RC = ln (1.9955) t PLH = 0.69xRxC = 0.69x1000x = 6.9 n Sec

Formal Definitions of Propagation Delay (PD) of Inverter. I/P and Inverted O/P have Finite Rise and Fall Times. Also, Delay Time between I/P and O/P Waveforms. Usually PD is Specified by Average of t PHL and t PLH. And these measured at 50% of I/P and O/P waveforms. Transition Times are Specified using 10% and 90% points of (V OH – V OL )

Home Work All Problems of Section 1.7 Specially; Problem Nos.: 1.86 and 1.89

In Next Class We Will Discuss: Chap 3 Diodes Topics: 3.1 The Ideal Diode Chap 5 Bipolar Junction Diodes (BJTs) 5.10 Basic BJT Digital Logic Inverter