DAQ/Trigger System proposal for the Angra Neutrino Detector Herman Lima Jr (18 May 2006) Centro Brasileiro de Pesquisas Físicas

Scenario Neutrino detection 128 PMTs Data Acquisition and Trigger per channel 150  s (max) window per event VETO 110 scintillators Only Trigger Calibration VEM (Vertical Muon) 60 channels (from the top and bottom VETO scintillators) X&Y position decoding on top and bottom planes

Neutrino detection - block diagram Analog-to-Digital conversion Signal conditioning Buffers Trigger logic Control logic VME bus 250 MSPS sample rate 10-bit resolution 2 ms leading-edge discriminators high-speed FPGA(s) PMT integrated on the PMT base

Neutrino detection - buffers Signal conditioning VME bus PMT ADC 250MHz front buffer 2  s Control logic long buffer 2 ms GPS receiver GPS Antenna VETO Trigger logic

Neutrino detection - event timing Trigger_1 (positron)Trigger_2 (neutron) 150  s event window 1st pulse to long buffer (2  s) 2nd pulse to long buffer (2  s) 4  s window verifying VETO Long buffer capacity (per PMT channel):  ordinary situation: (1 event = 2 pulses)  4  s  500 events  unusual situation: (1 event = 4 pulses)  8  s  250 events

Neutrino detection - buffer timing Trigger_1 (positron) clock sample N ADC out trigger reg 4ns t1t1 N front buffer out N-500 t 2 =t 1 +20ns t 3  start of transfer to long buffer N-5 N+495 t 4  end of transfer 2s2s

Neutrino detection - devices Analog-to-Digital converter AD MSPS 12 bits DNL =  0.3 LSB INL =  0.5 LSB MSPS FIFO (long buffer) IDT72T ,288 x MHz FPGA (logic) Stratix II – EP2S15 12,480 LUTs 419,328 bits RAM 275 MHz FIFO

Neutrino detection - module standard: VME 6U one module: 16 ADC input 250 MHz buffer size per channel = 524  s 128 PMT channels => 8 modules required dedicated lines on P2 to receive VETO interrupt requests to indicate ‘almost full’ condition control / status registers (e.g.: number of events in a buffer) ADC FPGA BUFFER (16cm x 23cm) front panel P1 P2 VME bus

VETO system - block diagram FPGA Signal Conditioning Trigger logic and control VME bus scintillator Leading-edge discrimination front-end electronics

VETO system - logic FPGA TOP plane trigger signals (LVDS) BOTTOM plane X(top) = X(bottom) ? Y(top) = Y(bottom) ? AROUND volume scintillators VEM flag Any logic other flags

VETO system - module FPGA (16cm x 23cm) front panel P1 P2 LVDS input channels Standard: VME 6U One module: 2 connectors on the front panel 68 LVDS input channels (total) LVDS receivers to reduce I/O pins in FPGA 110 scintillators  2 modules required 26 input channels free for new ideas LVDS receivers LVDS receivers VME bus

DAQ/Trigger system - integration VME bus Analog-to-Digital conversion Signal conditioning Buffers Trigger logic Control logic 128 PMTs Signal Conditioning Trigger logic and control 110 scintillators Leading-edge discrimination VETO Neutrino detection

DAQ/Trigger system - cost estimation itempart numberdescription unitqtytotal (US$) 1 AD9230BCPZ-250ADC, 12 bits, 250 MSPS IDT72T20128L4BBFIFO, x EP2S15F484C5FPGA Stratix II EP2C5F256C7FPGA Cyclone II Orcad Unison Ultra SuiteCAD tool for system design Quartus IICAD tool for logic design Crate VME 6U + power supply PCB manufacturing Included: 1 crate VME 6U, CAD tools, complex devices, PCB costs for 10 modules Raw estimation ! Not included: other devices, cables, assembling, quality control of PCB...

14 That’s all for now. Thanks.