Position Sensitive Detectors in HEP Silicon Detectors for Tracking and Vertexing Status: Past and Present Detectors Challenges: Radiation Hardness (LHC) Thin Detectors 3D Detectors Challenges: Precision (e+e-) DEPFETs MAPS SOI Vertical Integration Conclusions and Outlook

Position sensitive detectors From Wikipedia, the free encyclopedia: A Position Sensitive Device and/or Position Sensitive Detector (PSD) is an optical position sensor (OPS), that can measure a position of a light spot in one or two-dimensions on a sensor surface. In particle physics we use this principle to measure - Impact point of ionizing particles (tracker or vertex detector) Or, in astronomy and photon science Conversion point of a x-ray photon Disclaimer: Most of the talk will be on tracking detectors, ignoring largely x-ray detectors Solid state devices other than silicon are ignored as well

Position Sensing Versus Imaging Can imagers be used as trackers and vice versa? e.g. typical imaging sensors like CCDs have been successfully used in trackers (SLD) Main difference: Imagers measure intensities (many photons) Trackers: single particles (MIPS) Imager Position sensor Occupancy 100% O(1%) Readout full frame zero suppressed Rate < kHz > 10 kHz ( O(10ns)) Dynamic range high low or binary Pitch <10µm >10µm Area small large (single chip) (tiles, buttable) However, new applications in x-ray imaging at synchrotrons may ask for very fast sensors Belle II PXD with 1% occupancy (simulated) XMM Newton X-xray astronomy Structure analysis with x-rays (CAMP at SCLS)

Principles of Silicon Detectors Introduction: Diode Depleted thickness: Signal: Capacitance (important for noise)

Principles of Position Sensitive Detectors Position Resolution: Segmentation Silicon Strip Detectors Resolution: (binary) (charge division, in the best case) double sided: 2-dimensional information however, ambiguities Pixel Detectors true 2-dim information without ambiguity Silicon Drift Detectors & CCDs and other exotic devices (resistive charge division..)

Readout Electronics Charge sensitive amplifier followed by shaper (RCCR) Thermal noise input FET: ~ C/t1/2 1/f noise: ~ FET parameters, independent of t Shot noise: ~( Ileak t)1/2

A real sensor/readout scheme….

Module Layout Strip detectors: wire bonded readout ASICs at module end

Layout: Pixel Detectors ATLAS (similar at CMS, ALICE): Readout ASIC bump bonded (flip chip) on sensor Rather large material overhead (ASICs, structural material, cooling, services Flip chip bonding ‘standard’ in industry However for pitch > 140 µm Cost driver! Trend for future upgrades Large rASICs

Some History Strips ~1980 NA11/NA32 (external electronics) Mark II (ASIC readout electronics) ~1990 LEP: ASIC, double sided detectors ~ 100 Si-sensors, <100k channels ~2000 CDF: 6m2, 700k channels Pixels: 1980: NA32 (CCDs) 1990: SLD (CCDs) 1994: WA94 (hybrid pixels)

LHC detectors ATLAS CMS ALICE LHCb Strips: 61 m2 of silicon, 4088 modules, 6x106 channels Pixels: 1744 modules, 80 x 106 channels CMS the world largest silicon tracker 200 m² of strip sensors (single sided) 11 x 106 readout channels ~1m² of pixel sensors, 60x106 channels ALICE Pixel sensors Drift detectors Double sided strip detectors LHCb VELO: Si Strips

Challenges: Radiation Damage Ionizing radiation: Oxide damage in SiO2 Creates positive charges at SiO2/Si interface Shifts threshold voltages of transistors Creates parasitic channels (‘shorts’) (e.g. in n-in-n and n-in-p sensors) Not any more a problem in modern DSM CMOS with extremely thin gate oxides still a concern of some new detector concepts (DEPFET, SOI) + + + + + + + + + + + + + + + + + + + + + + + n+ - - - - - - - - - - Electron accumulation layer

Radiation Damage Bulk damage Particle knock off lattice atoms G. Lindström et al, NIMA 466 (2001) Bulk damage Particle knock off lattice atoms (NIEL, non ionizing energy loss Mid gap generation levels increase of leakage current Doping change donor removal/acceptor creation Type inversion (n->p) Increase bulk resistivity and depletion voltage Shallow traps: Trapping of signal charge => signal loss

Trapping: reduce drift distance a) Thin sensors Can recover pre-irradiation CCE at moderate voltage Easy to manufacture However: small signal anyway b) 3D Sensors (Sherwood Parker NIMA 395 (1997) Vertical electrodes (etched into bulk) collect charge laterally Make use of full bulk thickness (large signal) Increased capacitance Non standard process

Detectors for e+e- colliders ILC/CLIC SuperKEKB SuperB Main emphasis is on precision: -> ultra thin detectors Radiation damage not as bad as at LHC/sLHC but still an issue Furthermore: high occupancy due to background => Monolithic detectors: DEPFET

Comparison ILC - superKEKB Belle II occupancy 0.13 hits/µm²/s 0.1 hits/µm²/s radiation 100 krad/year 1 Mrad/year Duty cycle 1/200 1 Frame readout time 25µs – 50µs 20 µs Pixel size < 25 x 25 µm² 50 x (50-100) µm² Belle II: more challenging than ILC! (background, radiation, power) tight schedule (2015) while ILC is beyond 2020 need to develop a complete detector system R&D for and experience with B factories will boost sensor technologies for linear colliders

Detector Concepts Hybrid Pixels: Pixel detector with bump-bonded electronics problems: power and material! CCDs: used very successfully in SLD charge generation in small epi-layer problems: power, speed , small signal DEPFETs: depleted bulk with integrated amplification MAPS: Monolithic Active Pixel Sensors: intergrated CMOS electronics using “standard” CMOS: problems: speed, small signal (epi, drift) SOI: use depleted handle wafer as sensor very non-standard process 3D integration: Integrate complex CMOS on depleted sensor Needs advanced technology CCD

DEPFET A charge q in the internal gate influences a mirror charge aq in the channel (a <1, for stray capacitance) This mirror charge is compensated by a change of the gate voltage: DV = a q / C = a q / (Cox W L) Id: source-drain current Cox; sheet capacitance of gate oxide µ: mobility (p-channel: holes) Vg: gate voltage Vth: threshold voltage Source Drain P-channel Gate Gate-oxide; C=Cox W L L W d Internal gate

Belle II PXD Control ASIC Read out ASIC Low mass ladder concept Sensor thinned to 75µm Readout ASIC outside acceptance Low power: air cooling within acceptance 0.2% X0 => good impact parameter resolution even at low momenta Two layer detector 8 Megapixel Read out in 20µsec Inner layer Outer layer # ladders 8 12 Radius 1.4 cm 2.2 cm Pixel size 50x50 µm2 50x75 µm2 # pixels 1600(z)x250(R-ɸ) Thickness 75 µm Frame/row rate 50 kHz/10 MHz 50 kHz/10 MHZ 19

DEPFET: Sensor Thinning ? Need thin (50µm-75µm) self supporting all silicon module Wafer bonding SOI process Thinning of top wafer (CMP) Processing etching of handle wafer (structured) Process backside e.g. structured implant 450mm 50mm Cut through the matrix diodes and large mechanical samples diodes and large mecanical samples Belle II module

CMOS Sensors CMOS Sensors are used as optical sensors e.g. in digital cameras replacing CCDs Advantage: Combine sensor, amplifier and processing on one chip Cheap (CMOS) Modification to use as particle tracker R. Turchetta (2000) n-well used for signal collection only p-well possible for FET (n-MOS) no p-MOS transistors (only in periphery) Charge collection by diffusion in thin epi-layer (slow, small signal) Successful prototypes (MIMOSA series, IPHC) S/N: >20/1, Resolution < 2 mm

CMOS Sensors: MAPS MIMOSA 26 EUDET telescope STAR vertex detector Latest: MIMOSA 26 (IPHC Strasbourg) 576 x 1152 pixels, 18.4 µm pitch 13.7 x 21.5 mm² (active: 10.6 x 21.2 mm²) In pixel CDS Discriminator and 0-suppression in periphery High resistivity substrate (1 kOhmcm) Used in the EUDET telescope (thinned, 50µm) Evolution for the STAR vertex detector: 928 x 1152 pixels, 20.7 µm (almost twice the size) Frame readout time: 180 µs Thinned to 50µm STAR ladder: 0.37% X0 170mW/cm²: air cooling EUDET telescope STAR vertex detector

Advanced CMOS Sensors Digital section Analog section Deep N-well sensing electrode P-well N-well NMOS PMOS P-type epilayer or substrate 2D CMOS technology triple well, deep p-well => full CMOS possible (complex, fast) but still suffers from slow collection of small signal (VIPIX) High resistivity epi (IPHC) from XFAB 1 kWcm -> ~ 14 µm depleted Charge collection within 5 ns INMAPS (RAL): deep p-well shields PMOS completely High resistivity substrate (1-10 kWcm) 10-20 µm depleted Charge collection within 5 ns Remark: with complex electronics power becomes a problem

SOI Make use of SOI (silicon on insulator) technology Handle wafer: Detector grade silicon Top wafer: CMOS electronics Advantage: (thick) depleted sensor: -> large signal -> fast charge collection CMOS: separated by BOX -> full CMOS process -> PMOS & NMOS transistors Problems Back gate effect Radiation damage of (thick) BOX Project by KEK with ROHM Lapis semiconductor/SOITEC very non-standard high res (0.7 kOhmcm) handle wafer deep implants in handle wafer (back)

3D Interconnection Basic Problem: How to integrate good sensors and good electronic circuits? 3D Interconnection: Two or more layers (=“tiers”) of thinned semiconductor devices interconnected to form a “monolithic” circuit. Different layers can be made in different technology (BiCMOS, deep sub-m CMOS, SiGe,…..). Inherently offering thin chips & high interconnection density (= small pitch) 3D is driven by industry (continue with Moore’s law, increase speed, reduce power) HEP tracking detectors can profit from this R&D => Pioneered at Fermilab (R. Yarema), 3DIC collaboration (Tezzaron) Si pixel sensor BiCMOS analogue CMOS digital

Advantages even for single layer Conventional Layout 3D Layout Periphery, column logic, services Pixel area Make use of smaller feature size (gain space) -> move periphery in between pixels (can keep double column logic) -> backside contacts with vias possible -> no cantilever needed, 4-side abuttable

Ongoing R&D (examples) MPI Munich: innterconnection of ATLAS FEI3 with EMFT SLID technology (eutectic bonding) and tungsten vias (3 x 10 µm) Interconnection with 100% yield has been achieved. TSV to follow Bonn University: Backside connectivity of ATLAS FEI3 tapered vias by IZM 95 µm diameter Bump bonding Demonstrator working Essential: FEI3 available on wafers! AIDA WP3: R&D network for 3D interconnection: several technologies will be assessed (IZM, EMFT, LETI, T-Micro,.. using FEI4, Medipix, CMOS sensors…).

Support & Cooling 125 mm Self supported thin silicon: DEPFET: Monolithic device < 0.2% X0 Plume collaboration: double layer supported by SiC foam Aim for 0.3% X0 Both concepts rely on air cooling, excluding high density sensors with fast readout Need for active cooling adds material! Develop low mass support & cooling: INFN for superB Carbon tubes with liquid cooling 0.15 % X0 + sensor & flex 125 mm

X-ray Detectors Photon science at synchrotrons is booming! High intensity SASE light sources are challenging for detectors High dynamic range Short exposure time (XFEL: 200ns spacing) Many techniques and ideas used in HEP trackers can be used for x-ray sensors (hybrid pixel detectors) AND: there seems to be a market! Pilatus 6M, 12.5 Hz frame rate DEPFET based DSSC: 5 MHz frame rate

Summary Position sensitive silicon detectors have reached maturity and are an integral part of modern particle physics detectors LHC: large areas of silicon (up to 200 m2) radiation hard up to 1014 n/cm2 (strips) 1015 n/cm2 (pixel) Future need to improve by a factor of 10 ! Performance limited by trapping Promising concepts for >1016 n/cm² B-factories, linear collider: low mass, high resolution, high rate Integration of electronics and sensors a) Monolithic detectors b) 3D integration key for R&D: find industrial partner who is willing to adapt his process to our needs!

Pixel Detectors in HEP Hybrid Pixels sensors Monolithic sensors hybrid Two layers: sensor & electronic Fast, radiation hard Much material, power, large pixels Complex electronics Monolithic sensors Integrate electronics into sensor No interconnections Low mass Presently the complexity of the in pixel electronics is limited CMOS sensors (MAPS) ‘standard CMOS’ process use un-depleted epi layer as sensor small signal, slow charge collection DEPFET depleted bulk fast, large signal limited signal processing n p hybrid pixel ALEPH 1994 p n CMOS n n+ p DEPFET