Han Liu Supervisor: Seok-Bum Ko Electrical & Computer Engineering Department 2010-Mar-9.

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Han Liu Supervisor: Seok-Bum Ko Electrical & Computer Engineering Department 2010-Mar-9

Outline Information of literature Background Decimal Coding Partial Product Generation Multiplier Architecture Partial Product Reduction Comparison Conclusion 2

Information of literature Improved Design of High-Performance Parallel Decimal Multipliers Alvaro Vazquez, Elisardo Antelo, and Paolo Montuschi IEEE TRANSACTIONS ON COMPUTERS 2009 Nov. 3

Background Multiplication Operation Parallel and Serial Multiplication How to add the partial product together Tradeoff of Area and Latency 4

Decimal Coding 5 Fast ×5 and ×2 with coding conversion (no carry propagation) N_5211 × 2 (LS2) = 2N_4221 N_4221 × 5 (LS3) = 5N_5211

Partial Product Generation 1/3 6 For calculating X 10 × Y 10, we need {0, X, 2X, 3X, …, 9X}, this is called partial product SD Radix-10: convert Decimal set {0,…,9} to SD set {-5,…,0,…,5}, then Only {0, X, 2X, 3X, 4X, 5X} are needed to be implemented. SD Radix-5: Y=5 × Y U + Y L, then Only Y U set {0, 5X, 10X} and Y L set {-2X, -X, 0, X, 2X} are needed to be implemented.

Partial Product Generation 2/3 7 Radix-5 PP Generation

Partial Product Generation 3/3 8 Radix-10 SD PP Generation

Multiplier Architecture 9 Radix-10 Parallel MultiplierRadix-5 Parallel Multiplier

Partial Product Reduction 10

Comparison 11 [9] L. Dadda [20] T. Lang [ ] M. J. Schulte

Conclusion SD radix-10 and radix-5 parallel multiplication are interesting option for higher performance with moderate area For higher performance the choice is the SD radix-5 architecture, although both designs have very close figures. 12

Question Thanks! 13