VHDL Source Code for eP FIG Taiwan Conference February 17, 2012 Chen-Hanson Ting

Summary ep32_chip.vhdOverall Design ep32.vhdCPU of eP32 ram_memory.vhdMemory of eP32 uart.vhdSerial port gpio.vhdGeneral purpose IO ep32q_tb.vhdTestbench

VHDL Souce code I will scan the source code files so we have a general idea on what eP32 contains and how it is implemented. VHDL code is very portable so that you can move it to any FPGA chip or ASIC chip. eP32 is the simplest, yet most complete microprocessor design ever.

ep32_chip.vhd Define all external connections Define ports of all components Define signals connecting all components Instantiate all components

ep32.vhd Define IO ports of CPU Define internal signals and registers Define logic relations among signals Define instruction set Define finite state machine to execute instructions

ram_memory.vhd Instantiate DQ RAM memory modules. Initialize RAM memory contents to a FORTH dictionary. This module cannot be ported from one FPGA to another. It must be generated by tools provided by specific FPGA IDE. eP32 requires asynchronous RAM modules. Memory is mapped to 0-$00001FFF.

uart.vhd Instantiate a Universal Asynchronous Receiver Transmitter (USART). USART is initialized to 115,200 baud, 1 start bit, 8 data bits, 1 stop bit, no parity, and no flow control. It can be configures to other options. USART registers are mapped to $ x.

gpio.vhd Instantiate a 16 bit general purpose IO port. It includes these registers: Direction Register Input Register Output Register Registers are mapped to $E000000x.

ep32q_tb.vhd It is required by ispLEVEL to simulate eP32 chip. A template is provided by ispLEVEL. It is customized for eP32 chip. DIAMOND does not need a testbench. Signals in the eP32_chip top module can be customized to drive eP32 chip.

Conclusion CPU design is simple. Most CPU designers do not understand computer, and made their designs unnecessarily complicated. eP32 is the simplest, yet most complete microprocessor design ever.

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