New PSB Beam Control Upgrade of daughter cards Alfred Blas PSB rf Working group meeting 24/03/ Generation of REV clocks 2.Synchronization with Linac 4 3.Hardware and firmware upgrades

Generation of rev clocks Alfred Blas PSB rf Working group meeting 24/03/ Required: Clock signal at a high harmonic of the revolution What For?TFB, 1TFB, Q measurement, …. Specifications:up to 150 MHz, non-tagged, fixed harmonic DDS 1 GHz Freq./2 -> 50 % Duty Cycle < 160 MHz Tagged Clock NCO h LO < 20 MHz rf < 80 MHz Clk Freq. Div. + Tagging f MDDS Div.+ Dbl Tag < 160 MHz Clock Present rf creation setup SDDS

Generation of rev clocks Alfred Blas PSB rf Working group meeting 24/03/ The present rf creation circuit with a MDDS in cascade with a SDDS limits the output frequency to 20 MHz The creation of a high rev harmonic clock means using either: 1.A dedicated MDDS programmed to output a non-tagged clock 2.A dedicated SDDS channel + an external PLL 3.Using the second output on the MDDS to supply a non tagged < 80 MHz (or < 160 MHz) clock. 80 MHz at 1.4 GeV in the PSB would mean 28 MHz at 50 MeV and thus a bandwidth of the targeted digital circuit < 9 MHz. This is not sufficient. If the MDDS frequency was limited to 150 MHz, then the targeted circuits could cope with it (they are not yet designed, but this is the what ADCs can achieve with 14/16bit nowadays). In terms of flexibility and absence of new development, the dedicated MDDS solution 1) is preferred. Then comes solution 2) which means the creation of a specific PLL circuit and the use of a dedicated SDDS channel. The lastly chosen solution is 3) which requires some compromises (it is the less flexible).

Synchronization with Linac 4 Alfred Blas PSB rf Working group meeting 24/03/ Chopper ON/OFF Voltage modulation ΔE 4 rings 4 timing values for each injected turn Rev + 10* REV Number of turns + V H1 BIXi.SDIS Injection Sequencing control (IN BOR) To Linac rf feed-forward Application Linac rf Source Pre-chopper +LEBT 45 keV Distri 180 m 4*rf Debuncher Phase modulation Inj. rf reference (h1 or h2) Energy modulation Linac 4 Timing CO Inj. Ref Source BIXi.SInjChop BIXi.SInjRF

Synchronization with Linac 4 Injection Reference source Alfred Blas PSB rf Working group meeting 24/03/  The injection reference rf could be issued from the R1 LLRF (last ring that will stay at a fixed frequency until it comes to its turn), but there is not much to gain using this approach. The economy of one extra rf source would be obtained at the price of having R1 treated as a special case with no injection synchronization and a specific treatment within the injection sequencing control (ISC) because the injection in ring 1 would become the only case where the reference train could be used without applying the phase advance corresponding to the accelerating law

Hardware and firmware Upgrades Alfred Blas PSB rf Working group meeting 24/03/  DDC: The following changes require a new FPGA 1.Add 2 LOs 2.Add the signal monitoring circuit 3.Add FIR filters (?) 4.Add a couple of LEDs (Clock OK, …)  SDDS: The following changes require a new FPGA 1.Add the I/Q pre-programmed modulation circuits 2.Add a circuit that changes progressively each LO harmonic from one value to another (2 new registers: final h; number of clock tics for the ramping process + 1 control start bit) 3.Add the signal monitoring circuit 4.Add a couple of LEDs (Clock OK, …)  MDDS: The following changes don’t require a new FPGA 1.Make the tagging externally

Alfred Blas PSB rf Working group meeting 24/03/  General: b connector -> eSATA 3 Gb/s(?) This change required for a better mechanical reliability would mean to adapt all daughter cards + Fan-out. Because the eSATA connector is wider (21mm instead of 12 mm), this connector change would mean: On the MMDS: remove 2 SMC connectors (the 1 GHz in and out that have to be connected together) On the SDDS and DDC: remove the external reset input that is not used Hardware and firmware Upgrades