1 Hardware/Software Co-Design Final Project Emulation on Distributed Simulation Co-Verification System 陳少傑 教授 R 黃鼎鈞 R 尤建智 R 林語亭

2 Agenda 1. Introduction of verification 1. Introduction of verification 2. Simulation / Emulation 2. Simulation / Emulation 3. Principle of co-verification 3. Principle of co-verification 4. System Architecture 4. System Architecture 5. Experiment Result 5. Experiment Result 6. Conclusion 6. Conclusion 7. Reference 7. Reference

3 Introduction of verification Check if a design correctly implements specified behavior (usually done before manufacture) Check if a design correctly implements specified behavior (usually done before manufacture) Classes Classes Logic design verification Logic design verification simulation simulation emulation emulation formal verification formal verification Physical design verification Physical design verification

4 Challenge in SOC Era The complexity and gate count sky-rocket base on Moore Law The complexity and gate count sky-rocket base on Moore Law The chip includes multi-modules( IP ), and mixed signal blocks The chip includes multi-modules( IP ), and mixed signal blocks

5 Design and Verification Process Design : writing design specification and start design cycle Implement : Implement and refine the design through all phases Verify : Verify the Correctness of design

6 The Verification Bottleneck Verification problem grows even faster due to the combination of increased gate count and increased vector count

7 Approaches to Design Verification Software Simulation ─ traditional software-based simulation Hardware Accelerated Simulation ─ use special purpose hardware to accelerate simulation of circuit Emulation ─ Emulation actual circuit behavior Rapid Prototyping ─ Create a prototype of actual hardware Formal Verification ─ formal method

8 Simulation / Emulation Verification Software Simulation: With very high flexibility high extension and more cheaper than emulation Software Simulation: With very high flexibility high extension and more cheaper than emulation ----Verilog, VHDL, C/C++, mixed language Hardware Emulation: With very high speed for processing time Hardware Emulation: With very high speed for processing time -----PFGA, special hardware

9 Industrial Verification Issues Intel: Processor project verification: “Billions of generated vectors” “Our VHDL regression tests take 27 days to run. ” Sun: Sparc project verification: Test suite ~1500 tests > 1 billion random simulation cycles “A server ranch ~1200 SPARC CPUs” Bull: Simulation including PwrPC 604 “Our simulations run at between 1-20 CPS.” “We need cps.” Cyrix : An x86 related project “We need 50x Chronologic performance today.” “170 CPUs running simulations continuously” Kodak: “hundreds of 3-4 hour RTL functional simulations” Xerox: “Simulation runtime occupies ~3 weeks of a design cycle” Ross: 125 Million Vector Regression tests

10 Software Verification Mechanism Design Under Test Test Patterns Simulation Engine Monitor or Rule Check Library Specific outputs

11 System/Abstract level simulation Easily debug and diagnosis Easily debug and diagnosis Reduce simulation time Reduce simulation time 1. Saving data structure transfer time 1. Saving data structure transfer time 2. Native code predominance 2. Native code predominance Much more memory function Much more memory function HDL C/C++ Simulation Engine Perl HDL

12 Emulation System Advantages: + easiest to implement (involves little change to the simulation environment) + 10X to 100X faster than traditional simulation Disadvantages: --All module must be synthesized --Difficult to handle verification scripts or mathematical formulas --Can’t probe any signal we want (only on input/output)

13 SW/HW Co-Verification Dedicated hardware Software simulator Synthesizable DUT and transactor High-level protocol for Communication via network or system bus DUTTest Bench Design transactor Transaction- level HDL or C/C++ test bench

14 Principle of co-verification How to design an hardware / software co- verification system ? How to design an hardware / software co- verification system ? ----The key issue is PARTITION

15 Partition constraint on hardware part Maximum gate-count of FPGA or emulator Maximum gate-count of FPGA or emulator Maximum number of input and output ports Maximum number of input and output ports Maximum number of registers in FPGA or emulator Maximum number of registers in FPGA or emulator Gate-count balance among emulators Gate-count balance among emulators Delay for critical path in emulator Delay for critical path in emulator Monitored signal is suitable in hardware Monitored signal is suitable in hardware

16 Partition constraint on software part Communication overhead among simulators and emulators Communication overhead among simulators and emulators Monitored signal is suitable in hardware Monitored signal is suitable in hardware Tight clock policy or loose clock policy (multi-clock system) Tight clock policy or loose clock policy (multi-clock system) ALL of these are test patterns related factors

17 Partition process flow --Dynamic process HDL file Test Patterns Partition Engine Hardware constraintSoftware constraint Emulator Simulator

18 Incentives of the Project Provide earlier verification in IC design process Provide earlier verification in IC design process Co-verification among different level description Co-verification among different level description Physical Physical Register Transfer Level Register Transfer Level Behavior Behavior Accelerates verification Accelerates verification

19 Our Goal Verilog VHDL C Partition Manual/Automatic Simulate 1 Simulate 2 Emulate 1 Emulate 2 Co-verification

20 System Architecture (I) Distributed Simulation Distributed Simulation Master Child I Child III Child II TCP/IP port communication TCP/IP port

21 Features of the Simulator A master process A master process must be setup to manipulate communication must be setup to manipulate communication Several child processes Several child processes Each corresponds to one part Each corresponds to one part Communication Communication TCP/IP ports TCP/IP ports

22 Potential Difficulties (I) Distributed Simulation Distributed Simulation Synchronization Synchronization Different simulating speeds among parts Different simulating speeds among parts The faster have to wait The faster have to wait Data communication Data communication Communication overhead Communication overhead Partition Partition Clocks are the bottleneck Clocks are the bottleneck Duplicate global clocks within each parts speedup simulation Duplicate global clocks within each parts speedup simulation

23 System Architecture (II) Emulation Emulation Master Simulation Child I Simulation Child III Simulation Child II TCP/IP port FPGA Emulation

24 Features of the Emulator Must be child processes Must be child processes Each corresponds to one part synthesized as EDIF Each corresponds to one part synthesized as EDIF Under the control of a corresponding child simulation Under the control of a corresponding child simulation Communication Communication Through IDE to its corresponding simulation process Through IDE to its corresponding simulation process

25 Potential Difficulties (II) Emulation Emulation Synchronization Synchronization Among FPGA ’ s and Simulator Among FPGA ’ s and Simulator Clock Signals must be handled by Simulator Clock Signals must be handled by Simulator Among different FPGA ’ s Among different FPGA ’ s Simulator synchronize the verification progression Simulator synchronize the verification progression Data communication Data communication Must be manipulated by the simulator Must be manipulated by the simulator Multiple clocks Multiple clocks Handled by Simulator Handled by Simulator

26 Potential Difficulties (III) Design Partition Design Partition Manual / Automatic Manual / Automatic Emulation parts must be synthesizable Emulation parts must be synthesizable Hardware constrains Hardware constrains Communication overhead Communication overhead Among different emulation parts Among different emulation parts Among different simulation parts Among different simulation parts

27 System Limitation Emulation Emulation Clocks are handled by Simulator, emulation can progress one clock cycle at each call. Clocks are handled by Simulator, emulation can progress one clock cycle at each call. FPGAs works interruptedly instead at their full speeds. FPGAs works interruptedly instead at their full speeds. Partition among emulation parts may dominate communication overhead. Partition among emulation parts may dominate communication overhead.

28 Experiment Results RTL module : Jazz2020 (DSP core) RTL module : Jazz2020 (DSP core) Gate Count : 0.5M (estimated) Gate Count : 0.5M (estimated) Number of test patterns : 374 (with verification function) Number of test patterns : 374 (with verification function) Purely software simulation : 183 sec Purely software simulation : 183 sec Co-simulation (with Xilinx Vertex 400E) : 94 sec Co-simulation (with Xilinx Vertex 400E) : 94 sec Speed up : 2x (almost) Not fast as we expect Speed up : 2x (almost) Not fast as we expect

29 Future work We will separate RTL code into nonsynthesizable part and synthesizable part We will separate RTL code into nonsynthesizable part and synthesizable part Nonsynthesizable Part : Convert to C code (compiled code type) run under embedded CPU on FPGA chip Nonsynthesizable Part : Convert to C code (compiled code type) run under embedded CPU on FPGA chip Synthesizable Part : put into FPGA block Synthesizable Part : put into FPGA block Goal : All process will be done only on one FPGA chip Goal : All process will be done only on one FPGA chip

30 Future Work Original RTL code C Code non-synthesizable RTL Gate Level code Embedded CPU compiler FPGA synthesizer Embedded CPU Embedded CPU Compiled code netlist FPGA Block FPGA main board Partition Engine

31 Conclusion Simulation is and will be the most popular verification method. Simulation is and will be the most popular verification method. Emulation will standout as an accelerator under heavy simulation load. Emulation will standout as an accelerator under heavy simulation load.