1 Architecture and scalability of a high-speed traffic measurement platform with a highly flexible packet classification Author: Detlef Sas *, Simon Hauger,

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Presentation transcript:

1 Architecture and scalability of a high-speed traffic measurement platform with a highly flexible packet classification Author: Detlef Sas *, Simon Hauger, Martin Kohn Publisher: Computer Networks 53 (2009) Presenter: Han-Chen Chen Date:2009/10/28

2 Outline  Introduction  Traffic Measurement  Architecture of I 2 MP  Scalability of I 2 MP  Performance * I 2 MP (IKR Internet Measurement Platform)

3 Introduction  Evolving network technologies, new web services and changing usage patterns continuously change traffic characteristics. But a thorough understanding of the traffic is the basis for many applications in networking.

4 Traffic Measurement - purposes  network management  health monitoring  troubleshooting  accounting  network control  traffic characterization  modeling

5 Traffic Measurement - Functional blocks  Reception of data from the network link  Decoding line signal including error checks and restoring packets  Decapsulate packets from lower layer protocols  Time stamping  Pre-processing  Passive  Active  Storing data

6 Traffic Measurement - Platforms For processing data  General-purpose processors (GP-CPU)  Network processors (NP)  FPGA and ASIC For storing the measured data  HD  RAM

7 Architecture of I 2 MP

8 Hardware Unit Interface Time Stamping unit Classification and Filtering unit 1.decode protocol 2.classification packet 3.filter packet Assembly unit

9 Hardware Unit Classification and Filtering Unit

10 Hardware Unit Processing of a packet by Protocol Layering Decoder Protocol tag index

11 Hardware Unit Find the relevant criteria Find the all rules which contains these criteria Find the highest priority rule Classifier TCAM

12 PC Unit Online modeOffline mode 1.Reception of data containers 2.Post-processing of data records 3.Storage of the final trace

13 Scalability of I 2 MP Throughput of Hardware unit 1.Increase clock rate 2.Increase number of bytes processed in each clock rate Increase internal word width Replicate the entire system or those parts of limit the overall throughput 3.Process the first part of each packet Classification criteria and rules Increasing those parameters does not deteriorate the system ’ s throughput.

14 Performance 16 bytes word width Clock rate of 60MHz (FPGA) Packet size of 200Bytes Throughput of 20Gb/s (Ethernet, IP, TCP)

15 Thanks for your listening