FPGA Calculator Core Mid Presentation Chen Zukerman Liran Moskovitch Advisor : Moshe Porian Duration: semesterial November 2011

Contents Project Overview (+ Intro) Top Architecture Transition to postfix notation Micro Architecture Testability Next steps Schedule

Project Overview GUI FPGA Feedback Result Hardware implementation of calculator core : Positive integers Operands: ‘+’, ’-’, ’x’, ‘^’, ‘ { ‘, ‘ } ‘ Precedence rules compatible Manually acquisition Input via Matlab GUI Result display - LCD + debugging feedback 0.5 חן

Top Architecture Implemented integrated Next Step Intercon Wishbone TX PATH WNB2 WBS2 RX PATH WBM1 WBS1 CALC_CORE WBS3 WBM3 LCD_CORE WBS4 Altera Cyclone II FPGA LCD Display HD GUI - MATLAB Uart Out bits/sec Uart In bits/sec 0.5 חן

Intercon Wishbone TX PATH WNB2 WBS2 RX PATH WBM1 WBS1 CALC_CORE WBS3 WBM3 LCD_CORE WBS4 Altera Cyclone II FPGA GUI - MATLAB Uart In bits/sec Uart Out bits/sec LCD Display HD Implemented integrated Next Step SOP Type Address Data Length Postfix Data. FF Postfix Data. FF CRC EOP Infix - Data. FF Infix - Data. FF Postfix Data. FF Postfix Data. FF Infix - Data. FF Infix - Data. FF Infix - Data. FF Infix - Data. FF Result Type Address Data Length Result Type Address Data Length Result SOP Type Address Data Length CRC EOP Type Address Data Length Infix - Data. FF Infix - Data. FF Result Data Flow 1.5 חן

Previous calculator algorithm 5 x ( ^ 2 )( 5 x ( ^ 2 ) )( 5 x ( ) ) ( 5 x 10 ) 50 ( ( 5 5 x x ( ( ^ ^ 2 2 EOC ) ) ) ) 4 4 ( ( 5 5 x x ( ( ) ) ) ) ( ( 5 5 x x EOC ) ) 50 1 לירן

Problems with the algorithm Multiple read transitions in the RAM : Seeking for a specific operator each time and start the search again for every partial result calculated Multiple write transitions in the RAM: After each partial calculation the partial result is been written to the upper operand involved and shift all cells beneath the upper operand is required. By using the Postfix notation RAM actions can be reduced, calculation is simplified and system performance improved 0.5 לירן

The postfix notation benefits The postfix notation is a mathematical notation wherein every operator follows all of its operands. The postfix notation features are: parenthesis-free precedence rules are taken into account, in advance, therefore simplifies the calculation for example : (infix: 3 + 4) 0.5 לירן

Infix to postfix conversion Stack Infix: Postfix: 5*(6+2^2) 5* ( ^ > + precedence ^ 2 ^ + * 0.5 לירן

Micro Architecture 0.5 חן

Ram Charger Ram Charger receives the string data from WS and runs the data writing process in Ram1 Ram Charger operation is according to the following FSM diagram: 0.5 חן

Ram Charger in action 1 חן

Detailed View 0.5 חן

ACU - Algebraic Calculation Unit חן

Multiplier example (2x3=6) – wave view 0.5 חן

Operation Table Select valueHex codeBinary codeOperation ( ) ^ x FF End of Postfix\infix 0.5 חן

Runs and manages the core operation Produces necessary control signals in the right timing Operand Path Operator Path Final Result Path Calculator Core State Machine 1 חן

02 FF B B B FF 0B 1 Calculator Core in action detailed view 5 חן

Testability Testing and simulating environment : Goals : 1.functionality verification 2.verification that hardware and software calculation results are equal 0.5 לירן

GUI Method select Enter the exercise Exhibit the data to transmit Exercise display Software result Hardware result Gui messages 0.5 לירן

GUI-Video demonstration לירן

GUI-Video demonstration לירן

Text File String txt file format : General comment – desired test literally, explanation, Clarifications etc. Different notations comment: infix, postfix, postfix in hex + operator conversion Data line + expected result comment Postfix data Infix data End of postfix End of infix Expected result Wishbone signals TGA – Client TypeTGD – data length ADR – Client inner address 1 לירן

TextFile Text File Txt file example (3 strings): 0.5 לירן

String generator + checker Allows simple & fast testing and simulation Automatic feedback – message in the transcript window Working with multiple strings one after the other 0.5 חן

String generator + checker example Beginning of transmission End of transmission Data transmission process 1 חן

Operators blocks basic testing 32 bits 31 bits 32 bits 16 bits Power basic tests: Adder basic tests:Multiplier basic tests:Subtractor basic tests: 16 bits 1

General testing 0.5 חן

Next steps System integration with former project integrated blocks: RX, TX, wishbone etc. Implementation of result transmission from the Calc_core to the TX. Testing and Simulating in the top level after full system Integration. Synthesis + FPGA burning. Updating GUI to support the Uart protocol LCD Core implementation. 0.5 חן

Schedule TasksDate# Finishing PLL implementation cc_mdwm implementation + connecting Cores + TX adaptation Connecting gui to uart protocol to RX and from TX Top simulations Hardware burning to FPGA Upgrading cc_mdwm to support LCD LCD Core implementation Connecting all Cores + top simulations Hardware burning to FPGA Lab validation tests Project Book Final Presentation חן