CS/CoE 536 : Lockwood 1 CS/CoE 536 Reconfigurable System On Chip Design Lecture 7 : Demonstration of Machine Problem 2 : SPAM FILTER Washington University.

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CS/CoE 536 : Lockwood 1 CS/CoE 536 Reconfigurable System On Chip Design Lecture 7 : Demonstration of Machine Problem 2 : SPAM FILTER Washington University Fall Chris Neely, Chris Zuver Copyright 2002

CS/CoE 536 : Lockwood 2 Where to begin… MP2 distribution revisions: –Synthesis timing has been changed to 33 MHz – regex_sim.vhd added to simulate the content matcher This file is non-synthesizable regex.edn added to rad-xcv2000e directory which describes to the backend tools how to build the content matcher. –regex_sim.vhd added to “make compile” –Speed grade corrected to “-6” as opposed to “-7” –Simple INPUT_CELLS.DAT provided. Each student must create using the “IP Test bench” their own simulation traffic. Add wrapper_app.vhd from MP1 into MP2’s distribution in vhdl directory to begin MP2.

CS/CoE 536 : Lockwood 3 IP TESTBENCH ip2fake writes output cells in simulation format. Change INPUT_CELLS.TBP in the sim directory Convert to packets –make input_cells Add wait_10 manually before each cells in INPUT_CELLS.DAT # example IP packet !TCP srcip f6e73 6f6c c4c 204e4f # after IP2FAKE new_cell A DD E 54CCFC1C FE F6E73 new_cell F6C ………

CS/CoE 536 : Lockwood 4 HEX  ASCII Conversion The NCHARGE test website has been updated to include a HEX to ASCII converter. Ex. “Consolidate amazing”  436F6E736F6C D617A696E67 Available at fpx2.arl.wustl.edu/cs536fpx2.arl.wustl.edu/cs536 –Under “ACSII  HEX” link

CS/CoE 536 : Lockwood 5 Adding Content_Matcher Add component regex_app to wrapper_module.vhd Instantiate regex_app in wrapper_module.vhd Signals previously connected to wrapper_app No changes since MP1. wrapper_app New signals to connect reg_ex and wrapper_app together Reg_ex Wrapper_app

CS/CoE 536 : Lockwood 6 Sample VHDL architecture structural of my_module is component flop32 Port( clk : in std_logic; Din : in std_logic_vector(31 downto 0); Dout : out std_logic_vector(31 downto 0)); end component; … other components … Begin DataReg: flop32 port map ( clk => clk, Din => d_mod_in, Dout => d_mod_out); … other connections … end structural; --Note: Yalamanchili pp describe instantiation

CS/CoE 536 : Lockwood 7 Match Signal Only valid during sof=‘1’ Signal should be flopped before “reading” matched for timing. sof sof_flop match match_flop 8 8 Valid ExternalValid Internal

CS/CoE 536 : Lockwood 8 Ready & Enable Signals Each component signals an active ready_l signal when the component is initialized and ready to receive data. The wrappers asserts enable_l active to signal that all components are initialized. Data is now capable of being injected into the circuit. Wrappers Reg_ex Wrapper_app Ready_l ready_l enable_l

CS/CoE 536 : Lockwood 9 Completing MP2 Change wrapper_app.vhd –Accept “match” signal –Account for new control packet with updated payload –Update CAMs to handle new “match” cam entries.