Improving NoC-based Testing Through Compression Schemes Érika Cota 1 Julien Dalmasso 2 Marie-Lise Flottes 2 Bruno Rouzeyre 2 WNOC

2 Introduction NoC-based SoC n available access to each embedded core n efficient communication mechanism n reuse the NoC as Test Access Mechanism (TAM) SoC design n communication among cores n Network-on-chip SoC testing n access to cores n 1500 standard

3 NoC-based system SoC core Router Wrapper

4 NoC-based testing ATE SoC core

5 Reuse Model SoC core ATE

6 Reuse Model SoC core ATE

7 Reuse Model SoC core Wrapper: - test mode - basic 1500 modes

8 NoC-based Testing n Minimize total test time: –Maximize the use of network resources during test  Test scheduling techniques –Preemptive –Non-preemptive  Wrappers design –NoC protocol –1500-compliant

9 NoC-based Testing Approaches CUT packet header test header flit tail n Preemptive testing –One vector per message, non-reserved paths n Non-preemptive testing –All vectors in one message, dedicated paths

10 NoC-based Testing Approaches CUT packet header test header Slice 1 flit tail Slice 2 n Preemptive testing –One vector per message, non-reserved paths n Non-preemptive testing –All vectors in one message, dedicated paths –More than 1 scan slice per flit

11 NoC-based Testing Approaches CUT packet header test header Slice 1 flit tail Slice 2 n Preemptive testing –One vector per message, non-reserved paths n Non-preemptive testing –All vectors in one message, dedicated paths –More than 1 scan slice per flit

12 Reuse Model: number of Test Ports SoC core ATE = 2W channels w wwww  1 core under test

13 Reuse Model: number of Test Ports SoC core ATE = 4W channels w w ww w ww ww  2 cores under test

14 Test Time DfT Costs Number of Extra Pins p Inputs 79 Outputs 66 Bidirs 32 Cores

15 ATE Costs Test TimeNumber of ATE Channels p Inputs 79 Outputs 66 Bidirs 32 Cores

16 Problem How to increase the number of test ports Increase test parallelism Maximize NoC channels usage without increasing the ATE cost?

17 Goal Goal:  Use Horizontal compression to reduce the number of ATE channels required for each NoC test port, i.e. to increase the number of test ports How ?  Combine a horizontal compression scheme with a non–preemptive test scheduling approach to reduce test time

18 n Compression applied to NoC-based testing n Horizontal compression method n Test scheduling algorithm n Experimental results n Final remarks Outline

19 Compression Applied to NoC-based Test router wrapper N W Core W router wrapper W Core router wrapper W Core router wrapper W Core input W

20 Compression Applied to NoC-based Test Core i router wrapper Communication channels W W W decompressor FiFi W NoC Functional input pins M M≤ F i ≤ W

21 Compression Applied to NoC-based Test Core i router wrapper Communication channels W W W compressor FiFi W NoC Functional output pins M M≤ F i ≤ W

22 Compression Applied to NoC-based Test Core i router wrapper Communication channels W W W decompressor FiFi W NoC Functional input pins WkWk W k ≤ F i ≤ W n Each test port needs less than W bits  Less ATE channels per port  Increase the number of possible test ports  Increase test parallelism

23 Compression Applied to NoC-based Test n Horizontal compression –Test width reduction is the primary goal  Test vectors compression –Implies extra hardware at NoC-level (decompressor sharing) –May increase cores test time  Test responses compression –Implies extra hardware at NoC-level –Does not affect core test time

24 Horizontal Compression Techniques Test Data Compression ATE On-chip Decompressor Core M WW M W Scan Chains Compressed Test Data M < W n Compression applied to NoC-based testing n Horizontal compression method n Test scheduling algorithm n Experimental results n Final remarks Outline

25 Horizontal Compression: Requirements n Features  Circuit netlist independent (suitable for IPs)  Test data independent (additional test patterns)  Specific tools independent  Low cost hardware decompressor  No impact on fault coverage  Allow Shared decompressor for several cores

26 Horizontal Compression n Many published methods n Take advantage of Don’t Care bits (X’s) in test sequence n May increase core Test Time

27 Decompressor architecture W Add Cells Output Shift Register To scan chains From ATE M [1] Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre: Fitting ATE Channels with Scan Chains: a Comparison between a Test Data Compression Technique and Serial Loading of Scan Chains - DELTA 2006:

28 Decompression synchronization 00 Scan enable Control CLK S11000 S21001 S31110 S40110 S1 -> S2 : 0 1 S2 -> S3 : 1 1 S3 -> S4 : - - XXXX XXXX XXXX 1 0 X1X0 1 1 XXXX XXXX XXXX XXXX XXXX XXXX Original test Sequence Compressed test Sequence FSM Sc Sc Sc Sc Sc Sc 6 1 0

29 Compression Applied to NoC Data packet header test header tail Test pattern: Original test packet (W= 5) Compressed test packet (M = 2) packet header test header 01 tail 10 1X packet header test header packet header test header tail Uncompressed test packet (W = 5) compressor decompressor

30 Compression Applied to NoC-based Test Core Original Payload (32-bits) Comp. 32 -> 12 Comp. 32 -> n Example for d695 ITC’02 benchmark – uncompressed and compressed data (#flits) Compression may increase test time of individual cores

31 Compression Applied to NoC-based Test n Conclusion: ÞLocal increase in test time ÞIncrease test parallelism n Global test time reduction System ConfigurationTest time 1 32-bit input port36588 cycles 3 input ports of 12, 10, and 10 bits24395 cycles 32 ATE channels d Inputs 32 Outputs 10 Cores 33%

32 n Compression applied to NoC-based testing n Horizontal compression method n Test scheduling algorithm n Experimental results n Final remarks Outline

33 Test Scheduling Using Dedicated Paths  Each core is associated with a routing path  Includes input and output ports  All resources are reserved until test completed  Test pipeline maintained  No complex logic  Similar to a circuit switching  Efficiently assign I/Os and paths to core  Each input port leads to a different core test time [2] C. Liu, E. Cota, H. Sharif, D.K. Pradhan: Test Scheduling for Network-on- Chip with BIST and Precedence Constraints - ITC 2004: pp

34 Test Scheduling with Compression n Two test packets per core –Compressed test vectors –Uncompressed test responses n Pre-defined number of test interfaces –Number of inputs = number of outputs –List of I/O pairs n For each core and for each I/O pair –Input width changes (compression ratio changes) –size of input test packets pre computed

35 Test Scheduling with Compression Define test packets Define access paths for each core Select a core Find available access path Schedule packet

36 Test Scheduling with Compression Define test packets Define access paths for each core Select a packet Find available access path Schedule packet Packets sorted by probable test time

37 Test Scheduling with Compression Define test packets Define access paths for each core Select a packet Find available access path Schedule packet Select I/O pair that leads to minimal total test time Packets sorted by probable test time

38 Test Scheduling with Compression Define test packets Define access paths for each core Select a packet Find available access path Schedule packet If no path is found, try next core Select I/O pair that leads to minimal total test time Packets sorted by probable test time

39 Out  d695 from ITC02 benchmark  Channel width=32  3 inputs  10, 10, 12 bits  3 outputs  I/O pairs  3/9  6/7  8/ Test Scheduling Using Dedicated Paths In Out 10 12

40 Out Test Scheduling Using Dedicated Paths In Out

Out Test Scheduling Using Dedicated Paths In Out

Test Scheduling Using Dedicated Paths In Out

Test Scheduling Using Dedicated Paths In Out

44 Test Scheduling Using Dedicated Paths In Out

Test Scheduling Using Dedicated Paths In Out

Test Scheduling Using Dedicated Paths In Out

Test Scheduling Using Dedicated Paths In Out

Test Scheduling Using Dedicated Paths In Out

49 Out 9 Test Scheduling Using Dedicated Paths In Out

Test Scheduling Using Dedicated Paths In Out

51 Test Scheduling with Compression Define test packets Define access paths for each core Select a packet Find available access path Schedule packet Permutate cores Permutate I/O pairs

52 Experimental Setup n SOCIN Network –developed at UFRGS –grid topology –32-bit channels n ITC’02 SoC Test Benchmarks –Cores’ placement from design –Random test vectors (80% X's) n Test time versus ATE cost

53 System D695: 3 ports example System Configuration Test time (cycles) Number of ATE input channels 1 input port (32-bit) input ports (32-bit each) (-58.2%) 96 (+200%) 3 input ports (12, 10, and 10 bits) (-33.3%) 32 (+0%)

54 Experimental Results – d695 Test TimeNumber of ATE Channels d Inputs 32 Outputs 10 Cores

55 Experimental Results – d695 Test TimeNumber of ATE Channels d Inputs 32 Outputs 10 Cores

56 Experimental Results – d695 System Number of Inputs/ Outputs No CompressionWith Compression Test time (cycles) # of input ATE channels Test time (cycles) # of input ATE channels d695 1/ n/a 2/ / / /

57 Experimental Results – d695 System Number of Inputs/ Outputs No CompressionWith Compression Test time (cycles) # of input ATE channels Test time (cycles) # of input ATE channels d695 1/ n/a 2/ / / / same ATE cost - 65% test time reduction

58 Experimental Results – d695 System Number of Inputs/ Outputs No CompressionWith Compression Test time (cycles) # of input ATE channels Test time (cycles) # of input ATE channels d695 1/ n/a 2/ / / / Test time roughly equivalent - 50% ATE cost reduction

59 Experimental Results – g1023 System Number of Inputs/ Outputs No CompressionWith Compression Test time (cycles) # of input ATE channels Test time (cycles) # of input ATE channels g1023 2/ / / /

60 Experimental Results – g1023 System Number of Inputs/ Outputs No CompressionWith Compression Test time (cycles) # of input ATE channels Test time (cycles) # of input ATE channels g1023 2/ / / / % test time reduction - 20% ATE cost reduction

61 Final Remarks n Combination of NoC-based testing and horizontal compression –Reduces SoC test time –Reduces ATE costs n Compression technique –compliant with SoC Testing n Future works –seek for the best partition of ATE channels into test interfaces at NoC-level –test time reduction / area overhead trade-off

62 Thank You…