W.Skulski Phobos Workshop April /2003 Digital Pulse Processor DDC-8 (Universal Trigger Module) for PHOBOS. Wojtek Skulski University of Rochester

W.Skulski Phobos Workshop April /2003 Outline Trigger application in PHOBOS. Description of the Universal Trigger Module DDC-8. Two configurations: 1. Standalone module without DAQ readout. 2. VME front-end with DAQ readout. Response to scintillator pulses. Programming tools: FPGA programming tools. Embedded microprocessor tools. PC GUI programming environment.

W.Skulski Phobos Workshop April /2003 Vertex and centrality definition in real time Analog signals: Paddles, Cerenkov, ZDC. Logic signals from conventional NIM. 1st level processing: DDC. 2nd level processing: XLM, optional. Accept/reject event within about 1  sec. Online trigger Vertex definition from TACs. T0 OR  t, Paddle  t, ZDC  t. RHIC Centrality from paddle and ZDC.

W.Skulski Phobos Workshop April /2003 Possible configurations Standalone Universal Trigger Module DDC-8. 8 flash ADC channels + 41 logic I/O. Standalone data acquisition and histogramming. Counting House interfaces: USB and JTAG. Tunnel interface: RS-232. Real-time decision: fast. DAQ readout: no. The combo system UTM+XLM. 8, 16, 24, or 32 flash ADC channels + many logic I/Os. Real-time decision: slower due to “additional layer”. DAQ readout: yes. More complicated programming.

W.Skulski Phobos Workshop April /2003 Signal OUT 40 MHz * 10 bits JTAG connector micro processor FPGA ADC 40 MHz * 10 bits (8 channels) 16 bidirectional TTL lines + 1 in (fast parallel interface to XLM) Analog signal IN 8 channels with digital offset and gain control RS-232 Logic connectors NIM 16 lines IN, 8 lines OUT USB RAM 500 kB ECL clock IN (optional)

W.Skulski Phobos Workshop April /2003 Single channel 12-bit prototype, development and testing Input channel for waveform capture, up to 65 Msamples/s. Output reconstruction channel for development and diagnostic. The channel design to be used for the 12-bit multichannel board. Signal OUT JTAG connector USB processor connector FPGA Signal IN ADC 65 MHz * 12 bits Fast reconstruction DAC 65 MHz * 12 bits Variable gain amp

W.Skulski Phobos Workshop April /2003 ASC Nyquist filter ADC Sample rate processor Waveform memory Event rate processor Signal from preamplifier Clock Gain and offset control Optional external trigger analog digital Legend: ASC = Analog Signal Conditioning ADC = Analog to Digital Converter Trigger Pulse height and shape Individual trigger

W.Skulski Phobos Workshop April /2003 Analog section Digital section Correlation processor User-defined 17 I/O lines OR parallel interface Composite internal trigger Channel 1 Analog section Digital section Channel 2... Analog section Digital section Channel 8 Optional external trigger (one of the 16 NIM in lines) Internal triggers from channels 1…8 16*NIM in8*NIM out Analog section Digital section Channel OUT 17*TTL in/out

W.Skulski Phobos Workshop April / chan XLM MFLOPs 4 MB 40,000 gates DAQ 8 chan 32 flash ADCs 32*NIM out 8 chan 64*NIM in On-board monitoring 1.2 million gates in the FPGAs On-the-fly data preprocessing Four independent parallel interfaces, 100+ MB/s. VME Flash ADC front end

W.Skulski Phobos Workshop April /2003 # of analog input channels 8. # of analog output channels 1. # of logic inputs NIM 16. # of logic outputs NIM 8. # of in/out lines TTL Fast interfaces USB, parallel. Slow interfaces RS-232, SPI, I 2 C. Waveform memory 12  sec. On-board microprocessor 8 bits, 10 MIPS. Histogramming memory 0.5 MB. Packaging NIM, standalone. Intermediate scale: SuperBall+DwarfBall. Medium scale: PHOBOS trigger. Small scale: table-top DPP systems, student research projects, DPP algorithm development. DDC-8 features

W.Skulski Phobos Workshop April /2003 Response to scintillation pulses DDC-8 firmware is under development. Results obtained with DDC-1, bits. Very fast plastic BC-404: t pulse < t sampling. NaI(Tl): t pulse > t sampling. CsI(Tl): particle identification. Phoswich: two-component FAST-SLOW pulses.

W.Skulski Phobos Workshop April /2003 Signal from a Bicron BC-404 detector digitized with the 1-channel prototype at 48 Msamples/s * 12 bits Reliable digitization thanks to the antialiasing filter. Excellent response to a very fast pulse 1 sample = 20.8 ns1 sample = 0.2 ns Tek screen for reference Response to scintillator pulses: fast plastic scintillator A typical pulse in PHOBOS environment

W.Skulski Phobos Workshop April /2003 CsI(Tl) crystal cosmic ray phototube teflon Bicron BC-404 FAST SLOW Signal from a phoswich detector digitized with the DDC-1 48 Msamples/s at 12 bits FAST clearly separated from SLOW 1 sample = 20.8 ns

W.Skulski Phobos Workshop April /2003 Signals from a Bicron 2”x2” NaI(Tl) detector digitized with the 1-channel prototype at 48 Msamples/s * 12 bits 137 Cs Medium-fast scintillator pulses: NaI(Tl)

W.Skulski Phobos Workshop April /2003  -ray 1 cm 3 CsI(Tl) + phototube 1-channel prototype at 48 Msamples/s * 12 bits Note pulse shape dependence on type of radiation.  -particle Response to scintillator pulses: CsI(Tl)

W.Skulski Phobos Workshop April /2003  raditional slow-tail representation 1 cm 3 CsI(Tl) + phototube 1-channel prototype at 48 Msamples/s * 12 bits nat Th radioactive source PID = TAIL / TOTAL Note energy-independent PID Particle ID from CsI(Tl)

W.Skulski Phobos Workshop April /2003 Neutron Calorimeter SuperBall. 16 m 3 organic liquid scintillator. Online pulse shape analysis with DDC. Charged particle ID with CsI(Tl)/plastic. Neutron capture counting and timing. 1st level processing: DDC. 2nd level processing: XLM. Research application: SuperBall + DwarfBall 4  charged particle detector DwarfBall/DwarfWall. Plastic+CsI(Tl) phoswich detectors.

W.Skulski Phobos Workshop April /2003 Vertex and centrality definition in real time Analog signals: Paddles, Cerenkov, ZDC. Logic signals from conventional NIM. 1st level processing: DDC. 2nd level processing: XLM, optional. Accept/reject event within about 1  sec. Online trigger Vertex definition from TACs. T0 OR  t, Paddle  t, ZDC  t. RHIC Centrality from paddle and ZDC.

W.Skulski Phobos Workshop April /2003 Signal from a pocket NIM pulser digitized with the DDC-8 at 40 Msamples/s * 10 bits Excellent response to a very fast pulse seen with the “spy channel” t pulse < t sampling. Digitization made possible by the Nyquist filter f filter = 1/4 f sampling Latency = 300ns. Input pulse t ns How fast can we digitize the pulse?

W.Skulski Phobos Workshop April /2003 Time budget ADC pipeline latency: 9*12.5ns = ns. FPGA input: 25 ns. Nyquist filter: 100 ns. Tunnel -> CH propagation: 100 ns. Left-right time diff: 100 ns. TAC response: 300 ns. TOTAL = 0.74  s. Note: TAC output very likely can be made faster.

W.Skulski Phobos Workshop April /2003 Software and firmware development tools Entry-level software development. All development tools are free. FPGA: XILINX WebPack ISE. Embedded micro: Keil C compiler, code restricted to 4kB. PC GUI: Shareware edition of BlackBox Component Builder. Expert-level software development. All tools discounted for universities. FPGA. VHDL tools: XILINX ISE, full version. Graphical tools: MatLab and XILINX System Generator. Embedded micro: Keil C compiler, full version. PC GUI: Full edition of BlackBox Component Builder.

W.Skulski Phobos Workshop April /2003 Obstacles and showstoppers Obstacles. Firmware & software development takes time. Need an expert at the Phobos end. Only one board exists, two more being assembled, all are already booked. The 1 st board has not been fully tested yet. Showstoppers? Does Phobos need this tool? Can Phobos designate an expert? Recent deep cut in funding cannot be ignored.

W.Skulski Phobos Workshop April /2003 Summary The technology is under control. Glitches, if any, will be resolved. One DDC-8 assembled, works OK, but not yet fully tested. Two more boards being assembled. Firmware & software development will take time. A possible showstopper: recent cut in funding. Does Phobos need this device? My personal belief: if there is need, the expert will step forward. The situation looks good, but not hopeless.