LHCb front-end electronics and its interface to the DAQ

DAQ review Sep. 2001J.Christiansen/CERN2 Quick LHCb Front-end overview ~ 1 million detector channels. 10 different sub-detector front-end implementations. 40 MHz bunch crossing rate. –~1/3 has interaction Two trigger levels in front-end. –L0:4.0 us constant latency (pipeline buffer) Max 1.11 MHz accept rate –L1:Variable latency, max 1900 event (event FIFO) Trigger decisions distributed in chronological order 40 (100) KHz accept rate. Front-end architecture: –Simple front-end architecture where possible. –Central prevention of of buffer overflows. –Architecture extensively simulated in VHDL to insure correct function under all conditions.

DAQ review Sep. 2001J.Christiansen/CERN3 General architecture L0 buffer L0 derandomizer L0 buffer L0 derandomizer L0 Buffer L0 Derandomizer L0 Trigger + Readout Supervisor L1 Trigger + Readout Supervisor L0 buffer L0 derandomizer L0 buffer L0 derandomizer Zero Suppression & Multiplexing L1 Buffer L1 Derandomizer Output Buffer L1 Throttle L0 Throttle Front-End systemTrigger & TFC system L0 L1 L1 Trigger L0 TriggerTTC system DAQ

DAQ review Sep. 2001J.Christiansen/CERN4 L0 front-end L0 buffer L0 derandomizer L0 buffer L0 derandomizer L0 Buffer L0 Derandomizer L0 Trigger L0 Derandomizer Emulator L0 Trigger Raw 40 MHz L0 Throttle Readout supervisor 36 words = 32 ch + 4 tags 4 µ s 16 events 15 events Max MHz L MHz L1 Trigger system L1 Buffer Monitor Raw 40 MHz Constant latency: 4.0 us Maximum 1.11MHz trigger rate 16 events deep L0 derandomizer. Events from L0 derandomizer defined to be max 36 40MHz Derandomizer overflows prevented by central emulator in Readout Supervisor, based on a set of strictly defined front-end parameters.

DAQ review Sep. 2001J.Christiansen/CERN5 L1 front-end L0 buffer L0 derandomizer L0 buffer L0 derandomizer Zero Suppression & Multiplexing L1 Buffer L1 Derandomizer Output Buffer Reorganizer L1 Trigger + commands L MHz Readout supervisor 1927 events 15 events CPU L0 Throttle Nearly full Board System L1 Trigger 34 40MHz per word L MHz Max 40 (100) kHz L1 Trigger Derandomizer L1 Buffer Monitor Spacer Command 2 us DAQ L1 throttle

DAQ review Sep. 2001J.Christiansen/CERN6 L1 front-end Variable latency. L1 trigger decisions distributed to front-end in chronological order via TTC broadcast message. ( for both accepts and rejects) L1 buffers in front-ends implemented as simple FIFOs. L1 buffer occupancy monitored centrally by Readout Supervisor that throttles L0 triggers in case of risk of overflow. L1 trigger decisions sent to the front-end at a rate that can be handled by all front-ends (no local buffering of trigger decisions needed) 15 events deep L1 derandomizer: –3 events to handle L1 throttle delay (2us) –12 events for derandomization L1 derandomizer and following data buffers protected against overflow by hardwired L1 throttle signal. Zero-suppression (sparcification) and event data formatting.

DAQ review Sep. 2001J.Christiansen/CERN7 Centralized front-end control: Readout supervisor Receives L0 and L1 trigger decisions from trigger systems. Only distributes trigger accepts to front-end that will not generate buffer overflows. L0 derandomizer overflows prevented by L0 derandomizer emulator. L1 buffer overflows prevented by L1 buffer emulator. L1 trigger decisions spaced to match processing speed of front-end Buffer overflows in L1 derandomizer and following buffers prevented by hardwired L1 throttle network. Resets, calibration signals, testing and debugging functions. High level of programmability to allow system level optimizations. L1 buffer emulator L0 trigger L1 trigger derandomizer L1 trigger decision L1 decision spacer TTC encoder L0 throttle L1 throttle L0 derand. emulator TTC distribution L0 trigger decision L1 trigger

DAQ review Sep. 2001J.Christiansen/CERN8 Front-end control and monitoring Clock synchronous control of front-end handled by Readout Supervisor via TTC system. Local monitoring in front-ends of buffer overflows and event consistency based on event tags. ( Bunch ID, L0 event ID, L1 event ID). Error conditions sets error flags in event fragments and sets status bits to Experiment Control System (ECS). Front-end parameters down loaded via ECS system ( With enforced read-back capability ). Standardized ECS interfaces for front-end: –Credit card PC –SPECS ( simple serial protocol ) –CAN ELMB ( from ATLAS )

DAQ review Sep. 2001J.Christiansen/CERN9 Detailed front-end architecture

DAQ review Sep. 2001J.Christiansen/CERN10 Interface to DAQ Interface between front-end and DAQ system is handled by Readout Units. Standardized event formatting on optical links from front-ends. Data bandwidth per front-end branch limited to ~25Mbytes/s under nominal conditions to have headroom for unexpectedly high channel occupancies and allow upgrade from 40 to 100 KHz trigger rate. L1 FE FEM L1 FE FEM L1 FE FEM L1 FE FEM RU Sub-detector N Event building network N+1 L2/L3 CPU farm L1 Front-End electronics Front-End Multiplexing (optional) Readout Units Transport header Transport trailer Event building header Event building trailer Event data Event data header Event data trailer Event data Event data header Event data trailer Fragment 0 Fragment N Event formatting

DAQ review Sep. 2001J.Christiansen/CERN11 Data Link from front-end to DAQ Standardized unidirectional optical link handling distances of up to 100m. –No Xon/Xoff backpressure foreseen. In some sub-detectors the link transmitters are located in the cavern with limited levels of radiation (few Krad). Required bandwidth: 10 – 50Mbytes/s. Use of S-link enables: –Flexibility in choice of link technology. –Use of standardized link interface cards. Standardization on Gigabit Ethernet. –Defacto standard in computer industry. –Event building in DAQ will be based on Gigabit Ethernet. –Many relatively cheap components available. –Gigabit Ethernet S-link transmitter under development in Argonne. –Question of framing overhead: Event data is not heavily concentrated in LHCb. Reduced Ethernet framing can be used on data to Readout Units.

DAQ review Sep. 2001J.Christiansen/CERN12 LHCb Front-end in numbers DetectorChannelsFE linksFEMsLink RUsEvent size Vertex 205k MB/s76k RICH 450k55010 MB/s1515k Inner tracker 220k MB/s1411k Outer tracker 120k MB/s3039k Muon 26k1008 MB/s32k Calorimeter 20k MB/s1012k DIV 51k Total 1041k k