Details design ASIC test platform development By: Nadav Mutzafi Vadim Balakhovski Supervisor: Michael Yampolsky May 20091

DC to DC converter DC to DC converter Level translator Level translator PLL configurable PLL configurable FPGA implementation FPGA implementation May Topic points

May Voltages for I/O(1+2) Umodel 4604 : Umodel 4604 : ◦ Input voltage – 3.3V ◦ Output voltage - 0.8V to 3.3V ◦ Set by resistor ◦ current 4A, 5A peak ◦ High efficiency

May Voltages for core(3) Umodel 4604 : Umodel 4604 : ◦ Input voltage – 5V ◦ Output voltage - 0.8V to 5V ◦ Set by resistor ◦ current 4A, 5A peak ◦ High efficiency

May Voltages for core(4) LT1931 : LT1931 : ◦ Input voltage – 5V ◦ Output voltage – N5V ◦ Current – 350mA

May Voltages summary I/O voltages – two different I/O voltages – two different voltages from 0.8V-3.3V voltages from 0.8V-3.3V Core voltages – negative 5V, Core voltages – negative 5V, adjustable from 0.8V-5V adjustable from 0.8V-5V Connector for 5V and for another Connector for 5V and for another voltage from pc power supply. voltage from pc power supply.

May Level translator

May Level translator Auto bidirectional Auto bidirectional Supporting 100MHz Supporting 100MHz Determinist voltages : Determinist voltages : 1.2V, 1.5V, 1.8V, 2.5V, 3.3V 1.2V, 1.5V, 1.8V, 2.5V, 3.3V

May PLL configurable

May PLL configurable Programmable PLL, I2C Programmable PLL, I2C Crystal Frequencies 8MHz-54 MHz Crystal Frequencies 8MHz-54 MHz Six output clock(3.3V recommend) Six output clock(3.3V recommend) Power supply 3.3V Power supply 3.3V

FPGA Block Diagram

Tester IN module

Tester OUT module

Controller module FSMs: FSMs: ◦ Read – from DDR bank A to Tester IN ◦ DUT – from tester in to DUT to tester out ◦ Write – from Tester OUT to DDR bank B “Differentiator” “Differentiator” Buffering data from Tester IN Buffering data from Tester IN Bi – directional pins allocation Bi – directional pins allocation

FSM Read States: zero zero IS PAGE 1 AVAILABLE IS PAGE 1 AVAILABLE READING FROM PAGE 1 READING FROM PAGE 1 START DELAY PAGE 1 START DELAY PAGE 1 INIT COUNTER PAGE 1 INIT COUNTER PAGE 1 READ 1 READ 1 FINISH READ FROM PAGE 1 FINISH READ FROM PAGE 1 WHAT NEXT PAGE 1 WHAT NEXT PAGE 1 LOOP 1 LOOP 1

FSM DUT States: zero zero Sending Vectors Sending Vectors Hold Hold

FSM Write States: zero zero IS PAGE 1 AVAILABLE IS PAGE 1 AVAILABLE WRITING STATE PAGE 1 WRITING STATE PAGE 1 START DELAY PAGE 1 START DELAY PAGE 1 INIT COUNTER PAGE 1 INIT COUNTER PAGE 1 WRITE 1 WRITE 1 FINISH WRITE PAGE 1 FINISH WRITE PAGE 1

“Differentiator”

Buffering input vectors

Rates constrain Aim: 100Mhz * 96 = 9.6 Gbit/sec Aim: 100Mhz * 96 = 9.6 Gbit/sec PCI: 66Mhz * 32 = 2.1 Gbit/sec PCI: 66Mhz * 32 = 2.1 Gbit/sec Multi Port: 260*32 = 8.3 Gbit/sec Multi Port: 260*32 = 8.3 Gbit/sec

Bi-directional pins

Pinout constrain Max 96 input pins Max 96 input pins Max 48 Bi-directional pins Max 48 Bi-directional pins

FPGA future tasks Trigger support Trigger support Errors definition Errors definition System self test performance System self test performance I2C core I2C core