Advancing Optics with Physical & Link Layer Interoperability Steve Joiner OIF Technical Committee Chair Ignis Optics

Agenda  Mission of the Optical Internetworking Forum  OIF’s Strategy to advance optics  What are Implementation Agreements?  Published Implementation Agreements  Work in Progress  OIF at Supercomm2003

OIF’s Mission  Foster the development and deployment of interoperable products and services for data switching and routing using optical networking technologies.  Requires addressing multiple issues related to optical internetworking for Carrier System vendor Component vendor Integrated approach strengthens the OIF’s ability to fulfill its mission.

Strategy to Achieve Mission  Industry Driven Focus Carrier Voice in the technical committee Membership driven  Develop Implementation Agreements  Rapid Development controlled by a rigorous standards-like process  Working Group Organization Carrier Architecture Signaling OAM&P (security) Physical and Link Layer (PLL) Interoperability

Implementation Agreements  Narrowing the choices to a single profile  Create the “Glue Logic” that enables the commercial implementation of standards  Create new standards when needed

Do IAs advance the optics industry?  Improves development efficiency Collective wisdom prevails Reduces development mis-steps Results driven process required Technology providers make first solution selection  Improves adoption rate by industry Interoperability tests reduce risk Improves confidence in new technology  Improves system cost Creates competition Competitive edge driven by factors other than basic performance; i.e. price, efficiency, etc.  Improves time to market

Published IAs  Network control and signaling  Electrical interfaces  Optical interfaces  Optical multi-source agreement  Security  Critical non-IAs driving the industry Carrier Requirement Documents Liaisons to ITU, IETF, T1X1…

OIF Electrical Specifications

 SFI = SERDES to Framer Interface  SPI = System Packet Interface  TFI = TDM Fabric Interface  CEI = Common Electrical Specification Electrical Interface Architecture for the Data Path

SERDES Framer Interface (SFI) FEC Data Clock Data Clock OR SERDES Framer Interface (SFI) Optical Interface SERDES Device and Optics Data Clock Data Clock OIF Electrical Specifications Status Transmit Link Layer Device Receive Link Layer Device System Packet Interface (SPI) Data Status Data T F I PHY Device TDM Fabric to Framer Interface (TFI)

System Packet Interface (SPI-n) Transmit Link Layer Device Receive Link Layer Device PHY Device Data Transmit Interface Status Data Status Receive Interface System Packet Interface (SPI) S y s t e m t o O p t i c s O p t i c s t o S y s t e m OC-48 SPI lane path OC-192 SPI lane path SPI4-2 4 lane path OC-768 SPI lane path

OIF-SFI-4 phase 1 Electrical Interface S y s t e m t o O p t i c s O p t i c s t o S y s t e m Serdes REFCLK Framer FEC Processor TXCLK TXDATA [15:0] DC TXCLKSRC AB RXCLK RXDATA [15:0] AB TXCLKSRC AB RXCLK RXDATA [15:0] A B TXCLK TXDATA [15:0] DC The 300 pin MSA data interface

SerdesFramer FEC Processor REFCLK TXCLKSRC AB AB OIF-SFI-4 phase 1  OIF-SFI-4 phase 2 S y s t e m t o O p t i c s O p t i c s t o S y s t e m TXCLK TXDATA [15:0] DC Phase 1 TXCLK TXDATA [15:0] DC Phase 1 RXCLK RXDATA [15:0] A B Phase 1 RXCLK RXDATA [15:0] AB Phase 1

SerdesFramer FEC Processor REFCLK TXCLKSRC AB AB OIF-SFI-4 phase 1  OIF-SFI-4 phase 2 S y s t e m t o O p t i c s O p t i c s t o S y s t e m TXCLK TXDATA [3:0] DC Phase 2 TXCLK TXDATA [3:0] DC Phase 2 RXCLK RXDATA [3:0] A B Phase 2 RXCLK RXDATA [3:0] AB Phase 2

Capable of driving at least 8” of FR4 interconnect with one connector SerdesFramer FEC Processor OIF-SFI-4 phase 2 Electrical Interface 8"8" 8"8" S y s t e m t o O p t i c s O p t i c s t o S y s t e m TXDATA [3:0] DC TXCKSRC AB RXDATA [3:0] AB TXCKSRC AB RXDATA [3:0] AB TXDATA [3:0] DC REFCK

SFI-5 OC-768 SERDES to Framer Interface TXREFCK RXREFCK SerdesFramer FEC Processor TXDCK TXDATA [15:0] TXDSC TXCKSRC TXDCK TXDATA [15:0] TXDSC TXCKSRC RXREFCK DC A B DC AB RXDCK RXDATA [15:0] RXDSC RXS AB RXDCK RXDATA [15:0] RXDSC RXS A B Supports Forward Error Correction (FEC). EFEC GFEC S y s t e m t o O p t i c s O p t i c s t o S y s t e m

TDM Fabric to Framer (TFI-5) Reference Diagram TDM Switch Fabric SONET Framer TFI-5 SONET Framer FEC Processor SONET/SDH OC 3/12/48/192/768 G.709 OTN OTM 1/2/3 10GE LAN PH Processor 10GE LAN PHY SONET Signals Non-SONET Signals SONET Framer

Tunable Laser IAs  Tuneable Laser IA Classify Tunable lasers by application and features Protocol for Command; multiple interfaces Multiple mechanical feature options  Tuneable Laser MSA IA Specific set of choices from Tuneable Laser IA

Common Electrical I/0 (CEI)  Supercomm2003 – Introduction to market  Under Development by OIF  4 physical link interfaces 6+ Gbs Short ReachLong Reach 11+ Gbs Short ReachLong reach  Short reach Chip to chip Chip to module across one connector  Long Reach Backplane with two connectors  Data signaling for future interfaces Future SPI4 and SPI5 interfaces Future SFI4 and SFI5 interfaces Future TFI5 interface

OIF at Supercomm 2003  Superdemo Area  See interoperability demonstrations CEI 6+ G Long reach CEI 11+ G Short reach CEI 11+ G Long reach SPI-4.2 SFI-4.1 Tuneable Laser MSA UNI/NNI