2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt1 ITBB – Structure ProcessorMemoryInput/Output Bus device Processorexecutes instructions Memorystores information (data & instructions) I/Omoves data in/out of computer Businterconnects other components and supports interactions between them

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt2 ITBB: Fundamental Binary Assumption  all information is binary encoded result of transistor technology one bit = one binary digitvalue either 0 or 1 one Byte = 8 bits grouped together b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 e.g vs one word = machine dependent number of bits  information includes data and instructions! indicates base of number lsbmsb case!

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt3 Encoding (Representing) Data Using Binary Values  counting numbers  see Assignment 1  integers (format defacto standard)  floating point (IEEE standard)  characters (ASCII, Unicode)  boolean  days of the week  colours  other ??? later – Ch. 9 later – assembly language application / implementation dependent ( SYSC 2003 )

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt4  use some bits to encode operation  opcode  use some bits to encode operands (if present)  for now, assume fixed number of bits ( w ) per instruction fixed number of bits ( i ) used for opcode fixed number of bits ( j ) used for operand(s) Encoding (Representing) Instructions Using Binary Values opcodeoperands i bitsj bits w bits

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt5 ITBB Function  Recall functions in a computer: Data PROCESSING Data STORAGE Data MOVEMENT CONTROL  now we consider each component in terms of these functions and the roles of the components in the structure Function lecture 2

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt6 Processor ( a.k.a. CPU)  PROCESSINGarithmetic and logic unit ( ALU ) manipulates/changes/combines/calculates data values  STORAGEregisters hold values in CPU each register has a unique name  CONTROL control unit built-in instruction cycle  engine that drives machine instruction cycle drives control to memory and I/O components when appropriate ! CPU = Central Processing Unit

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt7 Processor Structure  MOVEMENT internal connections (control unit, ALU and registers) external Bus connections to other components ALURegisters Control Unit internal connections CPU external Bus connections

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt8 Processor Instruction Cycle START fetch instruction ( from memory ) execute the instruction HALT cycle may cause more memory accesses (for operands)

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt9 Memory ( 1 )  STORAGE fixed width locations (or cells) each location contains information – contents:the value stored in the location – address:unique “name” for each location  MOVEMENT internal connections external bus connections memory does not differentiate contents as instructions vs. data ( its all just binary values ) IMPORTANT SLIDE ! e.g. house numbers

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt10 Memory ( 2 )  PROCESSING(limited processing compared to CPU) refresh?  transistor technology  bit-level error checking? error correction ?  CONTROL (of memory actions) write – copy input value as new contents of a location read – output (but do not modify) contents of a location write / read driven from “outside” (e.g. processor, other ?) may provide external control  error condition? Ch. 5 later

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt11 Memory Structure memory processor locations Control Unit internal connections Memory external Bus connections

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt12 Input Output ( 1 )  function depends on connected devices  STORAGEfixed width registers (or ports) each register contains information – contents:the value stored in the register – address:unique “name” for each register  MOVEMENT internal connections external bus connections

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt13 Input Output ( 2 )  PROCESSING device dependent ! specialized hardware  CONTROL (of device-related processing) write – copy input value as new contents of a port read – output contents of a port not always the case that can read & write a port ! write / read driven from “outside” (e.g. processor, other) may drive external control  interrupts ! Ch. 7

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt14 Input Output Structure N. B. I/O component = Memory ! device processor registers ( ports ) Control Unit internal connections I/O external Bus connections device

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt15 Bus  pathway for interactions among components  standard signaling protocols for using the Bus specified using timing diagrams  MOVEMENTYES!  CONTROLarbitration (traffic cop) resolve concurrent requests to use the Bus  STORAGEnot usually  PROCESSINGnot usually Appendix 3A sometimes … arbiter

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt16 Putting ITBB Together - A “Simplified IAS-like” Example ( sIAS )  Want an example to show simple instruction execution  need details for: sIAS memory: locations sIAS processor: instructions, registers, instruction cycle  further simplification: assume decimal (instead of binary or hexadecimal) values  this example ignores: bus protocols, I/O, control details See IAS  Ch. 2.1, IAS-like, “Hypothetical”  Ch 3.1, 3.2

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt17 sIAS Memory location  contents: store 4-digit decimal values  address: a 3-digit decimal value since each address is unique  total address space = 1000 Memory address contents largest possible number of locations

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt18 sIAS Processor – Registers ALL reg’s hold 4 digit decimal values PC: address of next instruction to fetch IR: holding register for instruction after fetch AC:data register “accumulator” MAR: memory address register MBR:memory buffer register CPU Registers PC IR AC MAR MBR

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt19 1. Fetch Instruction  MAR PC // set up address for fetch  MBR Mem[ MAR ] // fetch instruction  IRMBR // save instruction  PCPC + 1 // set up for next fetch 2. Execute instruction in IR  may involve memory access sIAS Instruction Cycle means “gets loaded with” built-in sequential execution of instructions!!

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt20 4-digit Encodings Operation 1xxxLoad AC value from memory address xxx 2xxxStore AC value to memory address xxx 3xxxAdd contents of memory address xxx to AC = opcode encoding = operand encoding  Example instructions: if executed, what effect would these have on the CPU and memory? sIAS Processor – Instructions

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt21 Memory address contents Consider Example sIAS State CPU Registers PC IR AC MAR MBR...

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt22 1 st Instruction Cycle Iteration – Fetch 1.Fetch a)MAR 0225PC b)MBR1827Mem[ 0225 ] c) IR1827MBR d) PC0226PC + 1 instruction fetched:1827 Load AC value from memory address 827

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt23 1 st Instruction Cycle Iteration – Execute  execute instruction in IR:1827  Load AC value from memory address 827 a)MAR0827from IR b)MBR0001 Mem[ 827 ] c)AC0001from MBR

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt24 2 nd Instruction Cycle Iteration – Fetch 1.Fetch a)MAR 0226PC b)MBR3828Mem[0226] c) IR3828MBR d) PC0227PC + 1 instruction fetched:3828 Add contents from memory address 828 to AC Memory address contents

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt25 2 nd Instruction Cycle Iteration – Execute  execute instruction in IR:3828  Add value from memory address 828 to AC a)MAR0828from IR b)MBR0009 Mem[ 828 ] c)AC0010AC + MBR

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt26 3 rd Instruction Cycle Iteration – Fetch 1.Fetch a)MAR 0227PC b)MBR2828Mem[ 0227 ] c) IR2828MBR d) PC0228PC + 1 instruction fetched:2828 Store AC value to memory address 828

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt27 3 rd Instruction Cycle Iteration – Execute  execute instruction in IR:2828  Store AC value into location at address 828 a)MAR0828from IR b)MBR0010 AC c)Mem[ 828 ] 0010 MBR

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt28 Instruction Cycle - State Diagram access to memory no operands

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt29 Interrupts  Mechanism to interrupt normal sequence of processing  Why? I/O events: e.g. mouse click, network data arrives timer: e.g. animation program exception: e.g. overflow, division by zero hardware error: e.g. memory error  these are asynchronous events! require programmed service  events caused by hardware, not software instructions Ch. 7.4 Unpredictable timing

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt30 An Interrupt Scenario App. code interrupt handler (a.k.a. ISR) “driver”? independent execution contexts “threads of control” ISR = Interrupt Service Routine performs s/w action appropriate to interrupt event Suppose App. code executing: interrupt occurs want ISR to run then resume App. eg. editor eg. audio CD want to share processor between threads!

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt31 resume i+1 hardware invokes interrupt handler Transfer of Control via Interrupts App. code interrupt handler suspend thread ! interrupt occurs during execution of instruction at i

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt32  after instruction execute phase of cycle – processor checks: exception occurred? e.g. divide by 0 interrupt event signal input to processor?  If interrupt pending: Suspend and save context of current thread of execution Set PC to start address of ISR Continue Cycle  fetch 1 st instruction of ISR code  Eventually, ISR s/w restores context  resume interrupted thread  If no interrupt pending: Continue Cycle  fetch next instruction Extending Instruction Cycle for Interrupts done by processor h/w – no s/w !

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt33 Extending Processor Instruction Cycle START fetch instruction execute instruction HALT cycle interrupt pending no save context & set PC to start address of interrupt handler yes hmmmm….. last 3 slides all say the same thing

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt34 Digital Signaling  signals are indicated as voltage levels use particular levels to represent binary values –e.g. +5 volts  1 0 volts  0 change values “quickly” 1 0 time want to avoid reading when not stable signals stable Signals: “here is the data”, “read the contents of this address”, “I want to use the bus”, etc. Or could be –5V, 0V or…?

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt35 Signals and Timing Diagrams  often bundle groups of related signals as one in a timing diagram e.g. 16-bit addresses  16 address signals  one per bit 1 0 falling (trailing) edge rising (leading) edge 1 0 address signals may be stable, but do not represent a useful value signals stable, represent a useful 16-bit address App. 3A ~ ~ indefinite time elapsed

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt36 Bus  communication pathway connecting components  shared  communications broadcast to all on bus  organize communicated information into 3 groups: address data control of information being communicated everything else

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt37 Bus Interconnection Scheme memory I/O

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt38 Data Bus  carries data remember that there is no difference between “data” and “instruction” at this level  data bus width is a key determinant of performance 8, 16, 32, 64 bit

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt39 Address bus  identify the source or destination of data e.g. CPU needs to read an instruction (data) from a given location in memory  address bus width determines maximum memory capacity of system (address space) e.g has 16 bit address bus giving 64k address space 2 16

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt40 Address and Data Groups  often bundle address and data signals separately and use different physical pathways  may multiplex using same physical pathway 1 0 address 1 0 data 1 0 address data

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt41 Some Common Control Signals  reset – force all components to reset  clock(s) to synchronize communication  destination indicator – usually memory or I/O  acknowledgment from component – info received  interrupts  arbitration “hand shake”

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt42 Bus Protocols  signaling and sequencing to permit interactions between components processor puts address value on bus, and “memory read” control indication memory receives read signal, reads address, gets appropriate data, puts data on bus processor waits, then reads data from bus  May be Synchronous - synchronized by a clock – organize protocol by clock “ticks”  T i Asynchronous – no pacing by a shared clock e.g. memory read

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt43 T1T1 stable data E.G. Synchronous Memory Read T2T2 T3T3 clock addrs stable address mem read data T 1 initiate memory read (addrs, mem read) T 2 time for memory to do internal work T 3 data ready for reading from bus Assumption: Sensing of bus signals done during clock trailing edge

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt44 E.G. Asynchronous Memory Write no shared clock pacing the protocol mem write command processor memory

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt45 Single Bus Problems  lots of devices on one bus leads to: propagation delays –long data paths mean that co-ordination of bus use can adversely affect performance –if aggregate data transfer approaches bus capacity  most systems use multiple buses to overcome these problems evolution for performance!

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt46 Traditional bus (with cache) I/O Memory ProcessorCache: Remembers data from previous requests. Can processor request be answered from cache? If not  pass request on via system bus Ch. 4 aka Front side bus

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt47 High Performance Bus slower devices faster devices FireWire

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt48 PCI Bus  Peripheral Component Interconnection Bus  Intel released to public domain  32 or (optional) 64 bit address/data bus  49 mandatory lines  Note: 64 data 66 Mhz = 528 MBps = 4.2 Gbps  synchronous read bus on rising clock modify bus on falling clock rules for use !

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt49 PCI Bus Lines (required)  System lines including clock and reset  Address & Data (AD) 32 lines each: multiplexed interrupt & validate lines  Interface Control C / BE – command / byte enable: multiplexed  Arbitration  Error lines more optional lines too! text: table 3.3

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt50 PCI Commands  overview of a transaction between initiator (master) and target, e.g. CPU initiates a read from memory 1.master claims bus  arbitration & wait for idle 2.specify type of transaction e.g. I/O read/write 3.address phase( address & command ) 4.one or more data phases ( data & byte enable)

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt51 PCI Read Timing Diagram read bus on rising clock modify bus on falling clock

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt52 Some(!) PCI Signals – refer to text pg  xxx# - signal's active state occurs at low voltage  Frame# - Driven by current master to indicate the start and duration of a transaction.  Devsel# - device select. Asserted by target when it has recognized its address  C/BE[3::0]# - Multiplexed bus command and byte enable signals. During the data phase the lines indicate which of the four byte lanes carry meaningful data.

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt53 Some(!) PCI Signals -- refer to text pg 82-3  IRDY# - Initiator Ready. Driven by the current bus master. During a read indicates that initiator is ready to accept data. During write, indicates that valid data are on AD.  TRDY# - Target Ready. Driven by target. During a read indicates that valid data are on AD. During write, indicates that target is ready to accept data

2007 Sept. 18SYSC 2001* - Fall SYSC2001-Ch2and3.ppt54 PCI Bus Arbitration idle