OpAmp (OTA) Design The design process involves two distinct activities: Architecture Design –Find an architecture already available and adapt it to present requirements –Create a new architecture that can meet requirements Component Design –Design transistor sizes –Design compensation network

All op amps used as feedback amplifier: If not compensated well, closed-loop can be oscillatory or unstable. damping ratio  ≈ phase margin PM / 100 Value of  : Overshoot: 05%10% 16% 25% 37%

UGF: frequency at which gain = 1 or 0 dB PM: phase margin = how much the phase is above critical (-180 o ) at UGF Closed-loop is unstable if PM < 0 PM UGF

Two Stage Op Amp Architecture

z

GM<0 PM<0 p1 p2 z1 UGF

p1p2

PM GM p1p2z1 UGF

Types of Compensation Miller - Use of a capacitor feeding back around a high-gain, inverting stage. –Miller capacitor only –Miller capacitor with an unity-gain buffer to block the forward path through the compensation capacitor. Can eliminate the RHP zero. –Miller with a nulling resistor. Similar to Miller but with an added series resistance to gain control over the RHP zero. Self compensating - Load capacitor compensates the op amp (later). Feedforward - Bypassing a positive gain amplifier resulting in phase lead. Gain can be less than unity.

General Miller effect v1 v2= A V v1 i i = (v1-v2)/Z f =v1(1-A V )/Z f = - v2(1-1/A V )/Z f i = v1/Z 1 i= -v2/Z 2 v1 v2 i

Miller compensator capacitor C C C1 and CM are parasitic capacitances

DC gain of first stage: A V1 = -g m1 /(g ds2 +g ds4 )=-2 g m1 /(I 5 ( )) DC gain of second stage: A V2 = -g m6 /(g ds6 +g ds7 )=- g m6 /(I 6 ( )) Total DC gain: A V = g m1 g m6 (g ds2 +g ds4 )(g ds6 +g ds7 ) GBW = g m1 /C C 2g m1 g m6 I 5 I 6 ( )( ) A V =

Zf = 1/s(C C +C gd6 ) ≈ 1/sC C When considering p1 (low freq), can ignore C L (including parasitics at v o ): Therefore, A V6 = -g m6 /(g ds6 +g ds7 ) Z 1eq = 1/sC C (1+ g m6 /(g ds6 +g ds7 )) C 1eq =C C (1+ g m6 /(g ds6 +g ds7 ))≈C C g m6 /(g ds6 +g ds7 ) -p1 ≈  1 ≈ (g ds2 +g ds4 )/(C 1 +C 1eq ) ≈ (g ds2 +g ds4 )/(C 1 +C C g m6 /(g ds6 +g ds7 )) ≈ (g ds2 +g ds4 )(g ds6 +g ds7 )/(C C g m6 ) Note:  1 decreases with increasing C C

At frequencies much higher than  1, g ds2 and g ds4 can be viewed as open.  C1 C CLCL vovo Total g o at v o : g ds6 +g ds7 +g m6 C C C +C 1 Total C at v o : CL+CL+ C1CCC1CC C C +C 1 -p2=  2= C C g m6 +(C 1 +C C )(g ds6 +g ds7 ) C L (C 1 +C C )+C C C 1 

Note that when C C =0,  2 = g ds6 +g ds7 CLCL As C C is increased,  2 increases also. However, when C C is large,  2 does not increase as much with C C.  2 has a upper limit given by: g m6 +g ds6 +g ds7 C L +C 1 Hence, once C C is large, its main effect is to lower  1, and hence lower GBW. ≈ g m6 C L +C 1 When C C =C 1, w2 ≈ (½g m6 +g ds6 +g ds7 )/( C L +½C 1 )

Also note that, in contrast to single stage amplifiers for which increasing C L improves PM, for the two stage amplifier increasing C L actually reduces  2 and reduces PM. Hence, needs to design for max C L

There are two RHP zeros: z1 due to C C and M6 z1 = g m6 /(C C +C gd6 ) ≈ g m6 /C C z2 due to C gd2 and M2 z2 = g m2 /C gd2 >> z1 z1 significantly affects achievable GBW.

g m6 /(C L +C 1 ) f (I 6 ) z 1 ≈ g m6 /C gd6 A0A0 2 11 z 2 ≈ g m2 /C gd2 No PM

g m6 /(C L +C 1 ) f (I 6 ) z 1 ≈ g m6 /C gd6 A0A0 2 11 z 2 ≈ g m2 /C gd2 No PM z 1 ≈ g m6 /C c

g m6 /(C L +C 1 ) f (I 6 ) z 1 ≈ g m6 /C C A0A0 2 PM 11 g m1 /C C

It is easy to see: PM ≈ 90 o – tan -1 (UGF/  2) – tan -1 (UGF/z1) To have sufficient PM, need UGF <  2 and UGF << z1 In such case, UGF ≈ GB ≈ g m1 /C C = z1 * g m1 /g m6. PM ≈ 90 o – tan -1 (GB/  2) – tan -1 (GB/z1) Hence, need: GB <  2 GB << z1 PM requirement decides how much lower:

Possible design steps for max GB For a given C L and I tot Assume a current share ratio  i.e. –I 6 +I 5 = I tot, I 5 =  I 6, I 1 = I 2 = I 5 /2 Size W6, L6 to achieve max g m6 /(C L +C gs6 ) which is >  2 –C 1  W6*L6, g m6  (W6/L6) 0.5 Size W1, L1 so that g m1 ≈ 0.1g m6 –this make z1 ≈ 10*GBW Select C C to achieve required PM –by making g m1 /C C < 0.5  2 Check slew rate: SR = I 5 /C C Size M5, M7, M3/4 for current ratio, IMCR, etc

Comment If we run the same total current I tot through a single stage common source amplifier made of M6 and M7 –Single pole go/CL –Gain gm6/go –Single stage amp GB = g m6 /C L >g m6 /(C L +C 1 ) >  2 > g m1 /C C = GB of two stage amp Two stage amp achieves higher gain but speed is much slower! Can the single stage speed be recovered?

Other considerations Output slew rate: SR = I 5 /C C Output swing range: V SS +V dssat7 to V DD – V dssat6 Min ICM: V SS + V dssat5 + V TN + V on1 Max ICM: V DD - |V TP | - V on3 + V TN Mirror node approx. pole/zero cancellation –Closed-loop pole stuck near by –Can cause slow settling

When v in is short, the D 1 node sees a capacitance C M and a conductance of g m3 through the diode con. So: p 3 = -g m3 /C M When v in is float and v o =0. g m4 generate a current in i d4 =i d2 =i d1. So the total conductance at D 1 is g m3 + g m4. So: z 3 = -(g m3 +g m4 )/C M =2*p 3 If |p3| << GB, one closed-loop pole stuck nearby, causing slow settling!

Eliminating RHP Zero at g m6 /C C C C dv CC /dt v g = R Z C C dv CC /dt +v cc i cc = v g g m6 = C C dv CC /dt (g m6 R Z -1)C C dv CC /dt + g m6 v cc =0

For the zero at M6 and C C, it becomes z1 = gm6/[C C (1-g m6 Rz)] So, if Rz = 1/g m6, z1 →  For such Rz, its effect on the p1 node can be ignored so p1 remains as before. Similarly, p2 does not change very much.  similar design approach.

Realization of Rz vbvb

 V DD

Another choice of Rz is to make z1 cancel  2: z1=g m6 /C C (1-g m6 Rz) ≈ - g m6 /(C L +C 1 )  Rz = g m6 C C C C +C L +C 1 = g m6 1 (1+ ) C C L +C 1

Let I D8 =  I D6, size M6 and M8 so that V SG6 = V SG8 Then V SGz =V SG9 Assume Mz in triode Rz =  z (V SGz – |V T | - V SDz ) ≈  z (V SGz – |V T |) =  z (2I D8 /  9 ) 0.5 =  z (2  I D6 /  6 ) 0.5 (  6 /  9 ) 0.5 =  z /  6 *  6 V ON6 *(  6 /  9 ) 0.5 =  z /  6 *1/g m6 *(  6 /  9 ) 0.5 Hence need:  z /  6 *(  6 /  9 ) 0.5 =(C C +C L +C 1 )/C C

g m6 /(C L +C 1 ) f (I 6 ) -z 1 ≈ A0A0 2 PM 11 g m1 /C C

With the same C C as before –Z1 cancels p2 –P3, z3, z2, not affected –P1 not affected much –Phase margin drop due to p2 and z1 nearly removed –Overall phase margin greatly improved –Effects of other poles and zero become more important Can we reduce C C and improve GB?

g m6 /C L z 1 ≈ p2 A0A0 2 11 z 2 ≈ g m2 /C gd2 Operate not on this but on this or this z 4 ≈ g m6 /C gd6

Increasing GB by using smaller C C It is possible to reduce C C to increase GB if z1/p2 pole zero cancellation is achieved –Can extend to g m6 /C L –Or even a little bit higher But cannot push up too much higher –Other poles, zeros –Imprecise mirror pole/zero cancellation –P2/z1 cancellation –GB cannot be too high relative to these p/z cancellation Z2, z4, and pz=-1/R Z C C must be much higher than GB

Possible design steps for max GB For a given C L and I tot Assume a current share ratio  i.e. –I 6 +I 5 = I tot, I 5 =  I 6, I 1 = I 2 = I 5 /2 Size W6, L6 to achieve max single stage GB1 = g m6 /(C L +C outpara ) –Make z4=gm6/Cgd6 > (10~50)GB1 Choose GB =  GB1, Choose C C to make p2 ≈ GB/(10~20) Size W1, L1 and adjust  so that g m1 /C C ≈ GB –Make z2=gm2/Cgd2 > (10~20)GB Size Mz so that z1 cancels p2 –Make sure |pz| due to Mz and CC >> GB Make sure PM at f=GB is sufficient Size M3/4 so that gm3/CM is > GB/(10~20) Check slew rate, and size other transistors for ICMR, OSR, etc

Simple transistor circuits Can use any # of ideal current or voltage sources, resisters, and switches Use one or two transistors Examine various ways to place the input and output nodes Find optimal connections for –high gain –high bandwidth –high or low output impedance –low input referred noise

Single transistor configurations It’s a four terminal device Three choices of input node For each input choice, there are two choices for the output node The other two terminals can be at VDD, GND, virtual short (V source), virtual open (I source), input, or output node Most connections are non-operative or duplicates –D and S symmetric; B not useful

2 valid input choice and 1 output choice Connection of other terminals: or Resister

Capacitor Gnd or virtual Common source

To V DD This is D Source follower

N-channel common gate p-channel common gate

Diode connections

Building realistic circuits from simple connections N common source flip vertical  Combine 

N common source flip left-right  Combine to form differential pair 

flip upside down to get current source load   Combine to form differential amp V bb

Replace virtual gnd by current source  Can also use self biasing and convert to single ended output 

two transistor connections Start with one T connections, and add a second T Many possibilities –many useless –some obtainable by flip and combine from one T connections –some new two T connections Search for ones with special properties –in terms of A V, BW, r o, r i, etc

First MOST is CS D1 connects to D2: (with appropriate n-p pairing) v in vovo -kvo-kvo CS with negative gm at output node CSPush pull CS

V DD VxVx When V x = gnd T2 is not useful When V x = Vin, T2 and T1 are just one T When V x = -kV o what do we get? VoVo

V DD VxVx VoVo M1 M2 V x =gnd, M2 is I source V x = v in, ? V x = ─ v in, ? V x = v o, capacitor V x = kv o, negative g ds feedback

v in vovo -v in -v o kk V DD g m1 v in +g ds1 v o + g ds3 v o -kv o g m3 =0 M1 M3 M2 M4 M5 AV=AV= g m1 g ds1 +g ds3 -kg m3 A V =  when k = g ds1 +g ds3 g m3 GBW=g m1 /C o = GBW of simple CS

D1 connects to S2 V DD just a single NMOST V DD Cascode any benefits?

V DD Cascode with positive Vx feedback V DD Cascode with positive Vo feedback -kVx Vx Vo -kVo

V DD VoVo VoVo VoVo V in Folded cascode Effects on GBW?

V DD VoVo VoVo Vx -Vx -kVo-kVo folded cascode with positive feedback

V DD   V bb V in CLCL RbRb connecting D1 to S2  cascoding flip up-down for source    V bb V in CLCL   V yy V xx V DD

flip left-right to get this differential telescopic cascoded amplifier  V DD   V bb V in- CLCL     V in+ CLCL   V yy V xx  add M9 to change gnd to virtual gnd  GBW=g m1 /C o

How to connect G3 to –V x, –kV x, or – kVo   V in- CLCL     V in+ CLCL   V yy  V DD VxVx VoVo Same GBW Gain can be very high

How to connect G3 to –V x, –kV x, or – kVo   V in- CLCL     V in+ CLCL   V yy  V DD VxVx VoVo Same GBW Gain can be very high

V DD  V in CLCL  V bb V DD V in CLCL V bb flip up-down for I sources  connecting n-D to p-S

V DD V in+ CLCL V DD V in- V bb folded cascode amp Same GBW

V DD V in+ CLCL V DD V in- V bb How to connect for positive feedback?

D1 connects to G2, two stages V DD two stage CS amplifier CS amplifier with a source follower buffer

V DD Needs compensation and CM feedback Can gain be higher than single stage? Can GBW be improved vs single stage?

V DD VxVx -V x -v in Can you connect without loading effect?

V DD V omin = V in-min + V dssat or = V T + 3V dssat Biasing?

V DD V omin = 2V dssat But is the gain improved? Is GBW improved?

V DD VxVx VxVx V?V? Same as above, only T2 is pMOS Connecting S1 to D2 makes r o really small  buffer or output stage

V DD or

V DD  

connecting S1 to G2 V DD VxVx VxVx

VxVx Vx?Vx? 

connecting S1 to S2 VoVo -V in VoVo

connecting S1 to D2 V?V? V?V?

? ? e.g. 

M1 is common gate: D1 connects to G2 V in V DD

D1 connects to S2 V in

PSRR

V out = A dd V dd + A v (V 1 -V 2 ) = A dd V dd - A v V out  V out (1+A v ) = A dd V dd Good as long as Av >> 1, or f < GB

For zeros, set vdd = 0, vout float. This is the unity gain buffer configuration of the amp. Hence, char roots are: -GB and p2 DC gain: ignore all caps and find relationship between vdd and vout  at vout   gm1 at Id1  same at Id2   gm1/(gds2+gds4) at G6  vg6gm6/gds6 across DS6  vdd=  gm1/(gds2+gds4) *gm6/gds6 Vdd/vout = gm6 gm1/gds6(gds2+gds4)

For poles, make vout = 0, vdd float. Three nodes: S3/S4/S6, G3/G4/D1: ignore Write KCL at D2/D4/G6 node: v(gds2+gds4+sC I +sC C )=vdd(gds4+gds1*1) Current balance in M6: gm6(v-vdd)=gds6vdd  v=(1+gds6/gm6)vdd gds6/gm6*(gds2+gds4)+(1+gds6/gm6)s(C I +sC C )=0 gds6/gm6*(gds2+gds4)= -s(CI+sCC) Pole at - gds6(gds2+gds4) /(gm6(C C +C I ))

Similar computation for PSRR- 1.Get DC gain 2.Get zeros: they are the same as in PSRR+, and the same as poles of unity feedback Avd 3.Get dominant pole: Practice this, and see if you get similar results as in book

Two-Stage Cascode Architecture Why Cascode Op Amps? –Control the frequency behavior –Increase PSRR –Simplifies design Where is the Cascode Technique Applied? –First stage - Good noise performance Requires level translation to second stage Requires Miller compensation –Second stage - Self compensating Reduces the efficiency of the Miller compensation Increases PSRR