Renesas Electronics America Inc. © 2010 Renesas Electronics America Inc. All rights reserved. ID 416C:SH-2A Graphics for Low- to Mid-level Graphics Applications David Xu Field Applications Engineer 13 October 2010 Version: 1.2

2 © 2010 Renesas Electronics America Inc. All rights reserved. David Xu Field Application Engineer 12 years in automotive application area Assisted multiple automotive customers for graphics display developing projects Education BSEE from the Zhejiang University in China MSME from Wayne Sate University Work Experience Over 22 years experience with – Embedded control systems – Hardware design and software programming using MCUs – Plant automation systems

3 © 2010 Renesas Electronics America Inc. All rights reserved. Renesas Technology and Solution Portfolio Microcontrollers & Microprocessors #1 Market share worldwide * Analog and Power Devices #1 Market share in low-voltage MOSFET** Solutions for Innovation ASIC, ASSP & Memory Advanced and proven technologies * MCU: 31% revenue basis from Gartner "Semiconductor Applications Worldwide Annual Market Share: Database" 25 March 2010 **Power MOSFET: 17.1% on unit basis from Marketing Eye 2009 (17.1% on unit basis).

4 © 2010 Renesas Electronics America Inc. All rights reserved. 4 Renesas Technology and Solution Portfolio Microcontrollers & Microprocessors #1 Market share worldwide * Analog and Power Devices #1 Market share in low-voltage MOSFET** ASIC, ASSP & Memory Advanced and proven technologies * MCU: 31% revenue basis from Gartner "Semiconductor Applications Worldwide Annual Market Share: Database" 25 March 2010 **Power MOSFET: 17.1% on unit basis from Marketing Eye 2009 (17.1% on unit basis). Solutions for Innovation

5 © 2010 Renesas Electronics America Inc. All rights reserved. 5 Microcontroller and Microprocessor Line-up Superscalar, MMU, Multimedia  Up to 1200 DMIPS, 45, 65 & 90nm process  Video and audio processing on Linux  Server, Industrial & Automotive  Up to 500 DMIPS, 150 & 90nm process  600uA/MHz, 1.5 uA standby  Medical, Automotive & Industrial  Legacy Cores  Next-generation migration to RX High Performance CPU, FPU, DSC Embedded Security  Up to 10 DMIPS, 130nm process  350 uA/MHz, 1uA standby  Capacitive touch  Up to 25 DMIPS, 150nm process  190 uA/MHz, 0.3uA standby  Application-specific integration  Up to 25 DMIPS, 180, 90nm process  1mA/MHz, 100uA standby  Crypto engine, Hardware security  Up to 165 DMIPS, 90nm process  500uA/MHz, 2.5 uA standby  Ethernet, CAN, USB, Motor Control, TFT Display High Performance CPU, Low Power Ultra Low Power General Purpose

6 © 2010 Renesas Electronics America Inc. All rights reserved. 6 Microcontroller and Microprocessor Line-up Superscalar, MMU, Multimedia  Up to 1200 DMIPS, 45, 65 & 90nm process  Video and audio processing on Linux  Server, Industrial & Automotive  Up to 500 DMIPS, 150 & 90nm process  600uA/MHz, 1.5 uA standby  Medical, Automotive & Industrial  Legacy Cores  Next-generation migration to RX High Performance CPU, FPU, DSC Embedded Security  Up to 10 DMIPS, 130nm process  350 uA/MHz, 1uA standby  Capacitive touch  Up to 25 DMIPS, 150nm process  190 uA/MHz, 0.3uA standby  Application-specific integration  Up to 25 DMIPS, 180, 90nm process  1mA/MHz, 100uA standby  Crypto engine, Hardware security  Up to 165 DMIPS, 90nm process  500uA/MHz, 2.5 uA standby  Ethernet, CAN, USB, Motor Control, TFT Display High Performance CPU, Low Power Ultra Low Power General Purpose SuperH

7 © 2010 Renesas Electronics America Inc. All rights reserved. Innovation

8 © 2010 Renesas Electronics America Inc. All rights reserved. SH2A Graphic Display Solution Ideal for small graphic LCD (Up to WQVGA without external RAM) with few animations Integrated system solution with abundant on-chip peripherals High quality for automotive applications

9 © 2010 Renesas Electronics America Inc. All rights reserved. Agenda SH graphic display MPU Roadmap SH7262/SH7264 SH2A MPU overview Video display controller 3 (VDC3) module Application examples

10 © 2010 Renesas Electronics America Inc. All rights reserved. Key Takeaways Understand the structure of VDC3 Know functions of VDC3 Knowledge of using VDC3

11 © 2010 Renesas Electronics America Inc. All rights reserved. Roadmap ~ SH7264/62 * : Under Developing ** : Planning ***: Under Consideration SH7263 SH7751R SH-4, 240MHz PCI,SDRAM SH7268* SH-2A, 200MHz SH-2A,144MHz, 1MB/640KB SRAM SH-2A, 266MHz 2DG(OPENVG1.1), 2.5MB SRAM NTSC/PAL Decoder TCON ~ SH72xx*** SH-2A, 2DG, New NVM. NTSC/PAL Decoder Next Gen *** SH-4A Multi, 600MHz 3DG, DDR3/4 IMR, ASIL? SH7769** SH-4A, 533MHz, 3DG(OPGLES2.0), DDR3 SH7776* SH-4A Dual, 533MHz x 2 3DG,(OPGLES2.0), DDR3 SH7777** SH-4A, 533MHz, 3DG(OPGLES1.1 ),,DDR2 SH7266/67* SH- 2A,144MHz, 1.5MB SRAM SH7734** SH-4A, 533MHz, 2DG(OPENVG1.1), DDR2or3

12 © 2010 Renesas Electronics America Inc. All rights reserved. Features of the SH7262 and SH7264 SH2A 32-bit RISC CPU Core 144MHz Bus clock Superscaler structure On-chip large-capacity SRAM (1 MB) Reduce requirements for external SDRAM Dual frame buffers for display sizes up to WQVGA External SDRAM is still connectable. Abundant peripheral functions Display controller handles video input and TFT-LCD USB controller for High-Speed USB2.0 FPU, CAN, MTU2, and PWM timers for motor control Flash memory (NOR, NAND, serial flash memory etc.) is connectable.

13 © 2010 Renesas Electronics America Inc. All rights reserved. Overview Video display function Video recording function Graphic image overlaying function TFT-LCD panel control function

14 © 2010 Renesas Electronics America Inc. All rights reserved. Block Diagram

15 © 2010 Renesas Electronics America Inc. All rights reserved. Function Block Input timing control block Select timing of the sync signal Select timing of BT.601 and BT.656 video input signal Video receiving block Input video capturing, scaling, contrast, and brightness processing Converts YC format to RGB565 format, transfer data to memory via IV1-Bus Apply field skipping for record function Video supplying block Read data from memory via IV2-Bus Graphics block 1 Read graphics image (layer 1) from memory via IV3-Bus Overlay on the video data from video supplying block Output result to graphics block 2 Graphics block 2 Read graphics image (layer 2) from memory via IV4-Bus Overlay on the data from graphics block 1 Output result to panel control block Panel control block Generate sync signal for LCD panel Output timing control block Control timing of sync signal output Control timing of RGB565 video output signal

16 © 2010 Renesas Electronics America Inc. All rights reserved. Features (1)

17 © 2010 Renesas Electronics America Inc. All rights reserved. Features (2)

18 © 2010 Renesas Electronics America Inc. All rights reserved. Operations

19 © 2010 Renesas Electronics America Inc. All rights reserved. Input/Output Pins Video Input LCD Control

20 © 2010 Renesas Electronics America Inc. All rights reserved. Video Input Interface (1) BT.601 Video Input Sampling timing: Rising/Falling edge selectable Negative polarity supported

21 © 2010 Renesas Electronics America Inc. All rights reserved. Video Input Interface (2) BT.656 Video Input 525 lines 625 lines

22 © 2010 Renesas Electronics America Inc. All rights reserved. Video Display Function (1) Capturing

23 © 2010 Renesas Electronics America Inc. All rights reserved. Video Display Function (2) Video and Graphics Image Processing Flow

24 © 2010 Renesas Electronics America Inc. All rights reserved. Video Display Function (3) Conversion from YC to RGB

25 © 2010 Renesas Electronics America Inc. All rights reserved. Video Display Function (4) Conversion from RGB888 to RGB565

26 © 2010 Renesas Electronics America Inc. All rights reserved. Video Display Function (5) Relationship between Input Video Vsync and Reference Vsync

27 © 2010 Renesas Electronics America Inc. All rights reserved. Video Display Function (6) Controlling Video and Graphics Image Display Positions

28 © 2010 Renesas Electronics America Inc. All rights reserved. Video Recording Function

29 © 2010 Renesas Electronics America Inc. All rights reserved. Panel Control Signal Output Function (1) Sync Signal Generation

30 © 2010 Renesas Electronics America Inc. All rights reserved. Panel Control Signal Output Function (2) Data Enable Signal Generation

31 © 2010 Renesas Electronics America Inc. All rights reserved. Panel Control Signal Output Function (3) AC Modulation Signal (Alternating Signal)

32 © 2010 Renesas Electronics America Inc. All rights reserved. System Example Up to16 pins Line drivers BT.656/ 8-bit BT.601 Video decoder Other Video source/camera (NTSC/PAL) Data: 16pin NOR Flash Adr: upto 26pin SDRAM SH-2A CPU/FPU 144MHz ADC 8ch Bus I/F ROM,SRAM, NOR RTC DMAC 16ch RSPI 2ch (serial IF up to 36Mbps,1ch for serial flash boot) I2C 3chCMT 2ch RRAM:32KB SCIF 8ch WDT CAN 2ch IEBus 1ch MTU2 5ch NAND I/F (NAND boot available) 16bit Timer PWM 4ch Gauge control Up to 4 gauges LED Control I/O Sensors (Temp etc) EEPROM High, Mid CAN I/F and CAN wakeup Digital RGB565 SpeedTacho FuelTemp TFT Panel Size QVGA (320 x 240) TFT Panel Size QVGA (320 x 240) Serial Flash NAND Flash Data: 8pin Up to 8pins Up to12 PWM URAM (High speed) 64KB DCU Video Display Controller3 Line buffer 1 Line buffer 2 Line buffer 3 Video In USB VRAM (SRAM ) 1MB

33 © 2010 Renesas Electronics America Inc. All rights reserved. Example Case 1 - Driving Video Image on-chip SRAM 1MB 160KB Graphic Display Controller TFT panel output image OVERLAY CPU Video in Camera 240KB Line Buffer3 For Graphic2 Line Buffer2 For Graphic1 Line Buffer1 For Video Simultaneous Transfer to buffers 304KB DMAC PN D 12 Gas Ave. 20 MPG mile F E R P R ND12 Gas Ave. 19 MPG F E mile PN D 12 Gas Ave. 20 MPG mile F E R P R ND12 Gas Ave. 19 MPG F E mile Graphic program work area Graphic program work area HeadTail Graphic 1 For Picture

34 © 2010 Renesas Electronics America Inc. All rights reserved. Example Case 2 – Backup Monitor Video Image on-chip SRAM 1MB 160KB Graphic Display Controller TFT panel output image OVERLAY CPU Video in Camera 240KB Line Buffer3 For Graphic2 Line Buffer2 For Graphic1 Line Buffer1 For Video 304KB DMAC Graphic program work area Graphic program work area HeadTail Graphic 1 For Picture PN D 12 Gas Ave. 20 MPG mile F E R P R N D 12 Gas Ave. 19 MPG F E mile PN12 Gas Ave. 20 km/L km F E R D P R N12 Gas Ave. 19 km/L F E km D Simultaneous Transfer to buffers

35 © 2010 Renesas Electronics America Inc. All rights reserved. Example Case 3 – Backup Monitor & 2 Line Buffer Video Image on-chip SRAM 1MB 160KB Graphic Display Controller TFT panel output image OVERLAY CPU Video in Camera 240KB Line Buffer3 For Graphic2 Line Buffer2 For Graphic1 Line Buffer1 For Video 304KB DMAC Graphic program work area Graphic program work area HeadTail Graphic 1 For Picture PN D 12 Gas Ave. 20 MPG mile F E R P R N D 12 Gas Ave. 19 MPG F E mile PN12 Gas Ave. 20 km/L km F E R D P R N12 Gas Ave. 19 km/L F E km D Simultaneous Transfer to buffers Back:3.00 feet Warning! Back:0.01 feet Back:3.00 feet Warning! Back:0.01 feet HeadTail Graphic 2 For Character

36 © 2010 Renesas Electronics America Inc. All rights reserved. Questions?

37 © 2010 Renesas Electronics America Inc. All rights reserved. Innovation

© 2010 Renesas Electronics America Inc. All rights reserved. 38 Thank You!

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