Performed by: Yevgeny Safovich Yevgeny Zeldin Instructor: Yevgeni Rifkin המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering In-depth DSP QA 2002 סמסטר ( חורף ) שנה 1

Background המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 Cosmic waves influences on DSP Bits reversal in transistors because of radiation Any DSP module might be corrupted Malfunctioning localization General approach to DSP QA

Project goal המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 Develop testing environment Host PC used by an operator to: Run the tests Present results analysis Connection of host PC to DSP to: Load “active” testing routines Perform “passive” tests to verify proper functioning of standalone modules Localization of failures

Blocks Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 4 CPU o Control Registers o 6 ALUs o 32 A data path registers o 32 B data path registers CPU o Control Registers o 6 ALUs o 32 A data path registers o 32 B data path registers General o PLL o Interrupt controller o Boot configuration General o PLL o Interrupt controller o Boot configuration Peripherals o EMFIA o EMFIB o McBSP0 o McBSP1 o McBSP2 o Utopia o 3 Timers o HPI o GPIO Peripherals o EMFIA o EMFIB o McBSP0 o McBSP1 o McBSP2 o Utopia o 3 Timers o HPI o GPIO Buses o (E)DMA o Peripheral bus Buses o (E)DMA o Peripheral bus Internal Memory / Cache o L2 cache o L1 cache Internal Memory / Cache o L2 cache o L1 cache

Boundaries and Specifications המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5 3 main optional approaches: 1.Internal tests of the DSP – self test (executing a test program) 1.External tests – access DSP modules form outside to read/write data 2.Mixture of above 3’rd option selected for: Reliability, Complexity, Speed

6 Covered modules המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 Peripherals EMFIA, EMFIB, McBSP0, McBSP1, McBSP2, Utopia, 3 Timers, HPI, GPIO Buses (E)DMA, Peripheral bus, Internal Memory/Cache, L2 cache CPU Control Registers, 6 ALUs, 32 A registers, 32 B registers General PLL, Interrupt controller, Boot configuration

7 Uncovered modules, limitations המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 Cache L1 cache – tested as integral part of CPU Peripherals PCI TCP VCP

8 Solution architecture המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 DSP 6416 Control Program 90%

9 Solution architecture (cont.) המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 An external PC computer Execute/Control the tests Present the analyzed results Direct connection from host computer to DSP PCI cards to emulate peripheral interfaces (+device drivers) UTOPIA master McBSP master EMIFA EMIFB

10 Solution architecture (cont.) המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 “Passive tests” – external cross tests by host PC (Using host PC) “Active tests” – loading test routines to DSP The program will be executed on internal CPU The inputs will be taken from internal memory The results will be written to internal memory The outputs will be retrieved by the host PC through HPI To get most reliable result cross tests will be used (multiple units groups will be used for same tests)

11 Assumptions המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 L1 cache will not be tested separately A failure in major DSP modules cancels all next tests – such as: L1 cache internal memory HPI DMA Failure of HPI cancels all next tests (single direct access interface)

12 Open Issues המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 Direct communication between host PC and all DSP peripherals Most of the active tests should be written in assembler Most functions involve multiple modules (Especially in “active tests”) Slave ports – no cross connections DMA buffer – no direct access Error correction in peripherals – find a way to “corrupt data”

13 Schedule המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 15/08/02Feasibility and requirements study Design algorithms for testing of all modules except peripherals Design algorithms for testing of all peripherals Design global architecture 15/09/02Intermediate report Development of the control program Development of the tests routines running on the host PC Development of the tests routines running on the DSP Final integration 31/10/02Final report