WP2 Review Meeting Milano, Oct 05, /12/ MODERN ENIAC T2.5 Review Meeting WP2 and Tasks review Milano Agrate, 2011 Oct. 05 Meeting hosted by Micron 13:00 – 16:00 pm

WP2 Domain and Technology overview per task and partner Technologi es Process simulation Device simulation Electrical Charact. ReliabilityCompact Modeling Task Planar CMOS65nmUNCA 45nmUNGL POLI SNPS (STF2) IMEP STF2UNGLUNGL POLI STF2 NXP 32nmUNGL POLI (STF2) IMEP STF2UNGL STF2 NVM41nmUNET NMX SNPS UNET NMXUNET (NMX)UNET NMX FDSOIIMEP (STF2)LETI IMEPLETI Finfets, MUG, GAA STF2NXPIMEP HVMOSAMS TUW SiC, Power MOS STI AlGaN-GaN HEMT STI PV aware tools and methods are of common interest; they are developped and applied to a wide spectrum of technologies (Project book rev2 v2.4.1). Significant communalities of technology targets, except different ones for Process and Device simulation. (not funded) 2

T2.5 Task (2/1) Task T2.5: PV-aware compact modelling PV and reliability effects have to be implemented in device compact models to be able to accurately describe the impact of variability on circuit operation. Implementation methodologies will be worked out and adopted in standard compact modeling. Partners: UNET, AMS, LETI, NMX, NXP, POLI, STF2, ST-I, UNGL UNGL will develop compact model parameter extraction strategies that capture accurately the statistical device variability and the statistical aspects of reliability in industrial standard compact models including BSIM, BSIMSOI and PSP. POLI will be developing PV aware compact models in conjunction with the activities carried out in task 2.2, on the basis of the so-called sensitivity approach. The approach will be exploited for the development of quasi-static models (through the implementation of the DC sensitivity concept) and of dynamic models (through the implementation of the large-signal sensitivity concept). The strategy allows very efficient compact models, also accounting for the PV statistics, to be developed, also taking into account the correlation between different input parameters, provided that the input statistics is modelled in closed form. Such models will be deriving their parameters from physics-based simulations or characterizations. The modelling strategy will be mainly applied to the CMOS 45/32nm process, but can be taken into consideration for other technologies like GaAn/AlGaN power or RF devices as well. The compact models will be implemented within the framework of a suitable circuit simulation platform.The aim of the activity of ST-I is to develop a statistical Spice model for the design of complex nano-scale IC starting from TCAD simulations directly linked to process fluctuations due to equipments specifications. In this flow numerical techniques will be introduced in order to reduce the number of technology CAD simulations to be performed to extract the statistical model of a single device fabrication process and as consequence to reduce the computational costs and the time consumed; at the same time techniques will be used to reduce the number of circuit simulations for extraction of the statistical spice model of the IC, taking advantage of multi-objective optimization algorithm for yield analysis in addition AMS will implement reliability effects in device state of the art compact models in order to describe PV for circuit simulation in 0.35um, 0.18um and 0.13um CMOS and HV technologies. 3

T2.5 Task (2/2) Task T2.5: PV-aware compact modelling (cont’) STF2 will focus on the compact modelling of PV effects in bulk CMOS technology and application to the simulation of 45nm devices for circuit design. The work goes through classification of variability relevant sources, development of a formal description of process/device variables and associated compact models extensions in order to allow Monte-Carlo circuit simulation. The compact model extensions derived are intended to reflect systematic and random effects observed in a 45nm core CMOS technology at local scale (mismatch), intra-die scale, and interdie, and their layout dependence. NXP’s contribution will address a realistic physics based implementation method to mimic process variations as well as device fluctuations in analog circuit simulation using the PSP compact model. This will initially be done for all device types in a relatively mature 45nm CMOS node using the standard bulk CMOS PSP model. Subsequently, the methodology will be ported, adjusted and refined to more advanced and possibly 22nm bulk CMOS nodes. With further scaling it becomes mandatory to come up with viable analytical modeling approaches to efficiently incorporate new physics phenomena and their fluctuations in compact models, including quasi ballistic transport (QTB) features and the impact of variations of the dielectric thickness, channel doping and stress conditions, and with viable compact modeling approaches to reach the best trade-off between accuracy and statistics, including variability. UNET will address these aspects involving new physics for 45/32nm CMOS and for non-volatile memory technologies. NMX will in this task study a viable and effective implementation of an analytical compact model which takes into account PV in NVM logic devices (implementation of the characterization performed in WP2.3) and the impact random dopant, edge roughness, and trap position on scaled NVM cells; joint activities together with UNET are planned. Collaborations with ST-I and NMX are envisioned. Starting from BSIMSOI and an in-house PSP modified thin film device model, LETI will develop statistical modeling of the correlations between model parameters and variability sources for the FDSOI 22nm technologies. This will be used to classify and quantify FDSOI variability sources. 4

Compact Modeling: T2.5 Deliverables RefDeliverable/ ContributorsDue date D2.5.1PV-aware circuit-level models for standard CMOS technologies (down to 45nm) (UNGL, UNET, NXP, POLI, ST-I, STF2), and Non-Volatile-Memory technologies (NMX, UNET), and Discrete Power Device,SiC, GaN/AlGaN technologies (ST-I). State-of-the-art based statistical models, based on hardware and/or TCAD M18 Done D2.5.2Statistical PV-aware models for planar bulk CMOS generation devices (down to 32nm) (POLI, UNGL, UNET, NXP, AMS) M30 In progress D2.5.3PV-aware circuit-level models for 45nm analog 32nm CMOS technology (ST-F2) Modeling of additional variability sources of 3-dimensional device architectures, for new device architectures for 22nm (LETI, UNGL, UNET) M33 Request for change (STF2) Task Leader: Goal: focus of Task 2.5 “PV-aware Compact Modeling” is to implement PV and reliability effects in device compact models to be able to accurately describe the impact of variability on circuit operation (UNET, AMS, LETI, NMX, NXP, POLI, STF2, ST-I, UNGL. 5

D2.5.2 activities in progress D2.5.2 (M30)“Statistical PV-aware models for planar bulk CMOS generation devices (down to 32nm) (POLI, UNGL, UNET, NXP, AMS)” –Some partners already active (POLI, UNGL, UNET) –POLI will carry on PV aware compact modeling in conjunction with the activities carried out in T2.2 (on the basis of the sensitivity approach) extend to 32nm process –UNGL will create statistical compact model extraction strategies based on the comprehensive statistical simulation carried out in D2.2.4 investigate the sensitivity of compact model parameters for statistical compact model extraction investigate the accuracy of compact model parameters as a function of the statistical parameter set. apply PCA for width dependence of statistical parameter generation. –UNET has already completed and reported work on strain with NXP (paper at IEDM) will develop fast and efficient models for new physical effects in advanced MOSFETs (quasi ballistic transport) will work on Q.B.Transport with NXP Extremely efficient model for backscattering in nanoscale MOSFETs (elastic and inelastic) Fully calibrated and verified against Multi-Subband Monte Carlo simulations 6

D summary WP2 Review Meeting Milano, Oct 05, /12/2015 7

T2.5 publication list JOURNAL PAPERS N. Serra and D. Esseni, “Mobility Enhancement in Strained n-FinFETs: Basic Insight and Stress Engineering”, IEEE Transactions on Electron Devices, Vol.57, NO.2, pp , February 2010 A. Paussa, F. Conzatti, D. Breda, R. Vermiglio, D. Esseni and P. Palestri, “Pseudospectral methods for the efficient simulation of quantization effects in nanoscale MOS transistors”, IEEE Transactions on Electron Devices, Vol. 57, NO. 12, pp , December 2010 CONFERENCES J.-L.P.J. van der Steen, P. Palestri, D. Esseni and R.J.E. Hueting, “A New Model for the Backscatter Coefficient in Nanoscale MOSFETs”, European Solid-State Device Research Conference (ESSDERC), Siviglia (ES), settembre 2010, pp A. Paussa, F. Conzatti, D. Breda, R. Vermiglio, D. Esseni, "Pseudo-Spectral Method for the Modelling of Quantization Effects in Nanoscale MOS Transistors", Proceedings International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Bologna (Italia), settembre 2010, pag Workshops SISPAD workshop on Statistical Variability (UNGL) 2010, 2011 VARI workshop Montpellier L. Masoero, F. Bonani, F. Cappelluti, G. Ghione, “Modeling the effect of position-dependent random dopant fluctuations on the process variability of submicron channel MOSFETs through charge-based compact models: a Green's function approach”, Proc. VARI, Montpellier, 2010 F. Bertazzi, F. Bonani, S. Donati Guerrieri, G. Ghione, "Physics-BasedSmall-Signal Sensitivity Analysis for the Variability Aware Assessment ofDevices and Linear Analog Subsystems", Proc. VARI 2011, Montpellier, May

Task Review Summary Activity done so far, with highlights on technical results, and dissemination –Variability-aware Compact Models for Si CMOS and NVMs (parameter extraction and sensitivity evaluation) –Statistical models for specific physical mechanisms (development and calibration) Plan for next deliverables: –D2.5.2 is almost ready. Waiting for one more contribution (ask Ghione) –D2.5.3 due at M33: it seems on track Issues – no reply from some partners. Need to find more efficient « communication channels » Interaction need –Improve communications. Maybe check the contact list and indentify also some « active contributors » and not only « project contacts » List of papers and workshops updated –Little changes. –Remind to acknowledge MODERN 9

12/12/ WP2 Review Meeting Milano, Oct 05, 2011 T2.5 Task leaderPaolo Task participantsAlexander Jean-Rene Paolo Hans Giovanni Andre Valeria Angelo Ciccazzo ST-I Giuseppe Asen Gareth David Campbell CONTACT LIST T2.5 – before update

T2.5 back-up slides WP2 Review Meeting Milano, Oct 05, /12/

D2.5.2: UNGL contribution Statistical compact modelling (SCM) strategy featuring all variability sources is developed for variability-aware compact models in 32nm RVT N/PMOS. Direct extraction method based on statistical physical simulations is presented. Statistical model generation is developed for large-array circuit simulation.

SCM first-step: uniform model Uniform compact model is the base for statistical extraction, requiring expertise and experience.

SCM second-step: statistical extraction Vth0 – Threshold voltage of long- channel MOSFET U0 – Low field mobility parameter. Nfactor – Subthreshold swing factor. Voff– Offset voltage in subthreshold region for large W and L. Minv– Moderate inversion parameter. Vsat– Related to saturation velocity. Dsub– DIBL coefficient in subthrethold region. 1 parameter – Vth0 2 parameters– Vth0, U0 4 parameters– Vth0, U0, Nfactor, Voff 6 parameters- Vth0, U0, Nfactor, Voff, Vsat, and Dsub 7 parameters– Vth0, U0, Nfactor, Voff, Minv, Vsat, and Dsub Identified parameters for extraction Possible selections of parameters Select above parameters to extract statistical models from statistical simulations based on uniform models

Statistical extraction (cont.) More parameters to optimize, more accurate the model. 6 parameters extraction achieves almost the same accuracy with 7 parameters. NMOSPMOS

Statistical Model Generation

Statistical model generation (cont.) NPM based on high moments demonstrates capability to reproduce non-Gaussian distributed parameters.

Comparison of reproducing parameters

D2.5.3: Planned UNGL contribution Discover methods for extracting compact models form the novel devices studied in D2.2.5 Attempt to use the methodology used in D2.5.1 and D2.5.2 to extract statistical compact models fro the Novel device Architectures

D2.5.3: UNGL Progress Using BSIM Multi Gate the characteristics obtained from D2.2.5 have been replicated. Working to build an automated extraction strategy to allow statistical extraction

D2.5.3 ST contribution Goal: Statistical Compact Modeling methodology applied in 32nm planar CMOS technology –LP Mosfet devices –Intradie variations: statistical random + systematic Status of progress: 21 VariabilityTCADHW Electrical Characterization Compact Modeling StatisticalUNGL D224 (done) STF2/IMEP D233 (done) UNGL D252 from TCAD (done) STF2 D253 from HW (dec 2011) SystematicNASTF2 D253 (in progress) STF2 D253 from HW (dec 2011)