Architecture Selection of a Flexible DSP Core Using Re- configurable System Software July 18, 1998 Jong-Yeol Lee Department of Electrical Engineering, KAIST

Agenda Introduction MetaCore C Compiler MetaCore Assembler MetaCore Instruction Set Simulator “Compile-Simulate-Refine” Procedure of Architecture Selection Experimental Results Conclusion

Introduction Application-Specific Instruction set Processor(ASIP)  maximize the performance on a specific application  parameterized architecture Major issues in ASIP design  performance & cost efficiency instruction set & micro-architecture diverse exploration of the design space  short design turnaround time how efficiently transform the higher-level specification into lower-level implementation  application program development tools compiler, assembler, ISS(Instruction Set Simulator) Re-configurability

Introduction MetaCore is a flexible DSP core  MetaCore can be modified easily by just changing hardware parameters  MetaCore has special features for DSP applications(e.g. MAC unit and hardware loop unit) To support the flexible core  The system software must be re-configurable  For re-configurability, each software has its own form of machine description Using re-configurable system software  Many architectures can tested by iterating “compile- simulate-refine” cycles

MetaCore C Compiler(MCC) MetaCore C Compiler  Can be configured by changing parameters  Can be used to explore architectures Operation of MCC MCC Machine Description Application C Program main() {... m = min(m,t)... } : Parameter File A inst = 16bit general_ reg = 28 address_ reg = 8 minmaxALU = 0 Assembly Code A : Amin : cmp A0, R1 b.lt LLmin cla A0 add A0, R1 LLmin : mvtom *AR2(0), A0 : Assembly Code B : min A0, R1 mvtom *AR2(0), A0 : Parameter File B inst = 16bit general_ reg = 28 address_ reg = 8 minmaxALU = 1

Object Code 80 F0 AF 47 8F F MASM Assembly Code ADDA1, R7 SUB A0, R1 U_ADD A0, A1 B LOOP MetaCore Assembler(MASM) User can define new instructions  Mapping table is automatically reconstructed from Assembly Language Definition Operation of MASM Format Converter Format Converter Mapping Table Assembler // instruction : (operation field) (operand field) add : 80 (OP_ALU) sub : AF (OP_ALU) u_add : 8F (OP_ALU) Assembly Language Definition

MISS Object Code 80 F0 AF 47 8F F Instruction Usage Statistics Instruction Usage Statistics Program Output Program Output MetaCore Instruction Set Simulator(MISS) MetaCore Instruction Set Simulator  Enables fast simulation on instruction level  Supports re-configurability using Instruction Description Format  Can be used as a debugger of assembly codes Operation of MISS Decoding Tree Simulation Core Tree Builder U_ADD:B ,2,6 { Operands1 = GetSource 1; …. Result = AddOperands; SetConditionCodes; } Instruction Description Format

Compiler Architecture Selection Procedure Application C code Application C code Assembler Instruction-set Simulator Instruction-set Simulator Simulation Result Simulation Result OK? Architecture Refinement Architecture Refinement No Selected Architecture Yes “Compile-simulate-refine” cycle Architecture Parameter Architecture Parameter Assembler Language Definition Assembler Language Definition Instruction Description Format Instruction Description Format

Experimental Results Performance impact of accumulators  The reference architecture has six address registers and ten general purpose registers

Experimental Results Parameter selection considering generated code size  If the code size should be smaller than 32K bytes, 16 general purpose register and 4 address registers will be enough

Experimental Results Find minimum area under speedup constraints  Use simple iterative heuristic Speedup constraint Obtained area Optimal area Area overhead Number of iterations Benchmark ADPCM 5% 10% 15% 20% % 2.2% IDCT 5% 10% 15% 20% % 2.2% Viterbi 5% 10% 15% 20% % 17 16

Conclusion Present re-configurable system software for a flexible DSP core Show that the re-configurable system software can be used to select the most suitable architecture for a given application Code Optimization will be major future work