2011/IX/27SEU protection insertion in Verilog for the ABCN project 1 Filipe Sousa Francis Anghinolfi

SEU protection Goal: –Investigate high level SEU mitigation techniques with low power/area overhead and high effectiveness. To do: –Validate each SEU mitigation technique by simulation. –Power/area cost and effectiveness will be evaluated and compared after synthesis. SEU mitigation techniques: –Triplication –Hamming code –… 2011/IX/27SEU protection insertion in Verilog for the ABCN project 2

Triple mode redundancy Development of scripts to apply triplication in a given verilog module. Triplication is performed by creating three instances of the same module and connecting the output to a majority voter. Internal registers are also voted outside and are available again at the input of the triplicated instance. Triplicated clock lines are needed to avoid SEU in the clock lines to affect the circuit. The main disadvantages is that the power consumption and area overhead is on average 3 times more than the original design. 2011/IX/27SEU protection insertion in Verilog for the ABCN project 3 SEU_flag {output_signals, internal_reg_voted} {output_signals_1, internal_reg_out_1} {output_signals_2, internal_reg_out_2} {output_signals_3, internal_reg_out_3} input_signals internal_reg_voted internal_reg_out_1 inter_reg in clk internal_reg_out_2 inter_reg in clk input_signals inter_reg in clk input_signals Triplicated instance 1 Triplicated instance 2 Triplicated instance 3 Majority voter abcabc

Hamming encoding 2011/IX/27SEU protection insertion in Verilog for the ABCN project 4 Protect the registers from having its data altered due to an SEU. –assuming SEU duration small enough for not affect the combinatorial logic till the next clock cycle. Hamming encoding can be used in sequencers, or data/configuration registers to protect against SEU bit flips. It works by adding parity bits in order that two different codes\words differ at least in 2 bits [detection only] or 3 bits [detection and correction] Hamming encoding has a smaller overhead (≈X2) than the triplication technique (≈X3). –For up to 11 bits of data only 4 parity bits are needed Hamming encoding block (sequencers and store data) –Coding logic [combinatorial] –Register [sequential logic] –Decoding logic [combinatorial] Hamming encoding for case statements –For each case the parity bit are verified –If SEU detected the correct case is executed 7 bit Register Combinatorial logic Combinatorial logic Combinatorial logic Combinatorial logic Decoder logic 7 bit register coding logic 4 Parity bits Hamming encoding block

Hamming code 2011/IX/27SEU protection insertion in Verilog for the ABCN project 5 X 2 N X N (SEU) +1 (default) N is the number of bits in the state bits

SEU insertion in simulation The objective is validate by simulations the techniques proposed. –Insertion of SEU bit flips is needed during simulation. Time and effort is needed to insert manually SEU bit flips in a tesbench file. It is also error prone. From a practical point of view it is best to use the same testbenches used for functional tests also to validate the SEU mitigation techniques. –Thus reducing the time and effort of re-writing a testbench. A script can insert bit flips in selected registers during the test time. –The user can define also the time when the upset should occur in the register. 2011/IX/27SEU protection insertion in Verilog for the ABCN project 6

SEU insertion in simulation The script search for every register that can be upset and present the list to the designer The designer choose which register [or multiple] to upset The designer may also specify when in the simulation the SEU should occur Using the same testbench the comparison between a simulation with and without SEU is very practical using the a comparison tool from the simulator program. 2011/IX/27SEU protection insertion in Verilog for the ABCN project 7

Thank you … 2011/IX/27SEU protection insertion in Verilog for the ABCN project 8

2011/IX/27SEU protection insertion in Verilog for the ABCN project 9

Hamming code synthesis results 2011/IX/27SEU protection insertion in Verilog for the ABCN project 10 Normal FSMHamming code FSMX State bits3 bits 6 bits [3 state+3 parity] 2 #Cells Cell area Net area Leak power35,6 uW59,4 uW1.6 Switching power 121,0 uW314,9 uW2.6 Type cellsNormal FSMHamming code FSMX Sequential Inverters Buffer540.8 Logic Total