Vertex ‘99, 6/21-25/1999 p. 1 CDF Run II SiliconAlan Sill, Texas Tech University CDF Run II Silicon Tracking Projects 8th INTERNATIONAL WORKSHOP ON VERTEX DETECTORS Texel, Netherlands JUNE 1999 Presented by Alan Sill Department of Physics Texas Tech University

Vertex ‘99, 6/21-25/1999 p. 2 CDF Run II SiliconAlan Sill, Texas Tech University

Vertex ‘99, 6/21-25/1999 p. 3 CDF Run II SiliconAlan Sill, Texas Tech University l Increase acceptance and coverage of luminous region along beam äPrevious CDF vertex detectors covered interactions within |z| < 0.27 m, New silicon detectors designed to cover |z| < 0.43 m äInteraction region expected to be more concentrated in z in Run II äIncrease silicon angular acceptance to cover approximately   2. äOverall effect should be approximately a factor of 2 increase in acceptance for particles with good tracking and vertexing l Improve top tagging for high-p T physics: l Improve B physics capability of the experiment Goals for CDF Run II Silicon

Vertex ‘99, 6/21-25/1999 p. 4 CDF Run II SiliconAlan Sill, Texas Tech University CDF II Detector - Run II Configuration

Vertex ‘99, 6/21-25/1999 p. 5 CDF Run II SiliconAlan Sill, Texas Tech University Quadrant of CDF II Tracker LAYER 00

Vertex ‘99, 6/21-25/1999 p. 6 CDF Run II SiliconAlan Sill, Texas Tech University Fermilab Run II Silicon

Vertex ‘99, 6/21-25/1999 p. 7 CDF Run II SiliconAlan Sill, Texas Tech University CDFII Silicon Tracker: Layer 00 + SVXII + ISL Goals and Features: l Precise 3D track impact parameters äB tagging: top, SUSY, Higgs äB Physics l Improved forward coverage ä0    2 l Level II displaced-track trigger (SVT) äHadronic B decays äCalibration triggers l Improved p T resolution l High tracking efficiency with good purity

Vertex ‘99, 6/21-25/1999 p. 8 CDF Run II SiliconAlan Sill, Texas Tech University SVX3D R/O Chip Rad-hard 0.8 um Honeywell CMOS Tested to ~ 4 MRad Deadtimeless Dynamic pedestal subtraction Common to all Run II CDF silicon projects

Vertex ‘99, 6/21-25/1999 p. 9 CDF Run II SiliconAlan Sill, Texas Tech University SVX3D R/O Chip

Vertex ‘99, 6/21-25/1999 p. 10 CDF Run II SiliconAlan Sill, Texas Tech University Readout Chip Specifications *

Vertex ‘99, 6/21-25/1999 p. 11 CDF Run II SiliconAlan Sill, Texas Tech University SVX II Collaboration

Vertex ‘99, 6/21-25/1999 p. 12 CDF Run II SiliconAlan Sill, Texas Tech University SVX II: 3 Barrels, 5 Layers

Vertex ‘99, 6/21-25/1999 p. 13 CDF Run II SiliconAlan Sill, Texas Tech University SVX II vs. Previous Detector

Vertex ‘99, 6/21-25/1999 p. 14 CDF Run II SiliconAlan Sill, Texas Tech University SVXII Parameters

Vertex ‘99, 6/21-25/1999 p. 15 CDF Run II SiliconAlan Sill, Texas Tech University Silicon Specifications SVX II silicon sensor specifications for Hamamatsu (90 o layers 0,1, 3) and Micron (1.2 o layers 2, 4) *

Vertex ‘99, 6/21-25/1999 p. 16 CDF Run II SiliconAlan Sill, Texas Tech University SVXII Barrel Fabrication Fixture for installing SVX II ladders into barrel (precision aligned bulkhead pair) Test assembly with mock aluminum bulkheads and mechanically accurate ladders

Vertex ‘99, 6/21-25/1999 p. 17 CDF Run II SiliconAlan Sill, Texas Tech University SVX II Ladders SVX II half ladder, consisting of two silicon sensors wirebonded with the readout electronics mounted on the first sensor. Si Sensors Electrical Component Hybrid SVX3 Chips HDI cable Rohacell/Carbon Support Wirebonds Bridge Connection

Vertex ‘99, 6/21-25/1999 p. 18 CDF Run II SiliconAlan Sill, Texas Tech University Layer 00 Collaboration FNAL, INFN-Pisa, INFN-Padova, LBNL, Purdue,U.California-Davis, U. Florida, U. Glasgow, U. Liverpool

Vertex ‘99, 6/21-25/1999 p. 19 CDF Run II SiliconAlan Sill, Texas Tech University Layer 00 l Beam pipe layer of 1-Sided Silicon äImprove IP resolution - Better B tagging for higgs, SUSY äExtend useful lifetime äLong-term operational experience with LHC rad-hard silicon Resolution improvements:

Vertex ‘99, 6/21-25/1999 p. 20 CDF Run II SiliconAlan Sill, Texas Tech University Layer 00 Design Values

Vertex ‘99, 6/21-25/1999 p. 21 CDF Run II SiliconAlan Sill, Texas Tech University Layer 00 in SVX II 2.2 cm

Vertex ‘99, 6/21-25/1999 p. 22 CDF Run II SiliconAlan Sill, Texas Tech University ISL Collaboration FNAL, INFN-Pisa, INFN-Padova, INFN-Bologna, LBNL,Texas A&M, U.California-Davis, U.California-Los Angeles, U. Cassino, U. Florida, U. Karlsruhe, U. Rochester,U. Tsukuba, Osaka City University

Vertex ‘99, 6/21-25/1999 p. 23 CDF Run II SiliconAlan Sill, Texas Tech University Intermediate Si Layers äCDF ISL: Proposal and Conceptual Design (FNAL). Final Design (Pisa). - Emphasis on simplicity and low cost. äSpace frame manufactured in Italy; INFN Pisa & FNAL are the main production sites (roughly half each). CDF ISL

Vertex ‘99, 6/21-25/1999 p. 24 CDF Run II SiliconAlan Sill, Texas Tech University ISL Modules l Overview of Design äC Fiber substrate - All bond pads are accessible from both sides ä3 Sensors  m pitch (both sides) - Double Sided 1.2 o Stereo Angle äHybrid mounted off Silicon - 8 readout chips per hybrid l Module Production äMechanical Fabrication: - less than 2 hours äWirebonding: - 20 minutes per side (roughly 1 hour total w/setup) äTesting & Repair - Under study

Vertex ‘99, 6/21-25/1999 p. 25 CDF Run II SiliconAlan Sill, Texas Tech University ISL Ladder Assembly l Pilot production ladders äKarslruhe fixtures refined w/use l Hybrids äExpect all substrates end of summer äPrototypes operate as expected äFinal assembly limited by SVX3D availability

Vertex ‘99, 6/21-25/1999 p. 26 CDF Run II SiliconAlan Sill, Texas Tech University CDF Run II DAQ l Fully pipelined DAQ+Trigger architecture (396 -->132 ns) l Operates “deadtimeless” l One of our largest subprojects l Total board count >15,000. l ~100 different custom boards ä~ 35 High volume boards (qty >100) l For SVX3D, everything up to L1 accept is on the chip l SVT (not covered here) provides L2 displaced-track trigger

Vertex ‘99, 6/21-25/1999 p. 27 CDF Run II SiliconAlan Sill, Texas Tech University Silicon DAQ *

Vertex ‘99, 6/21-25/1999 p. 28 CDF Run II SiliconAlan Sill, Texas Tech University SVXII DAQ

Vertex ‘99, 6/21-25/1999 p. 29 CDF Run II SiliconAlan Sill, Texas Tech University ISL DAQ each HDI (and DOIM) has 16 chips — 4 per side on each of two ladder ends *

Vertex ‘99, 6/21-25/1999 p. 30 CDF Run II SiliconAlan Sill, Texas Tech University Final Assembly / Installation

Vertex ‘99, 6/21-25/1999 p. 31 CDF Run II SiliconAlan Sill, Texas Tech University Simulation: Run II CDF Si Open Inventor based ROOT based

Vertex ‘99, 6/21-25/1999 p. 32 CDF Run II SiliconAlan Sill, Texas Tech University Expected Performance Reported previously for SVX II, ISL Improvements with L00: Good overall top tagging Improved IP resolution More tracks In top b tag Should survive ~10 MRad

Vertex ‘99, 6/21-25/1999 p. 33 CDF Run II SiliconAlan Sill, Texas Tech University Conclusions l SVXII + ISL + L00 design provides complete silicon tracker that should give robust performance throughout Run II l Silicon on track for complete delivery by early to mid 2000 l Hybrid substrates complete (SVXII) or will be soon (ISL, L00); population in progress l SVX3D chip provides rad-hard deadtimeless operation l PROBLEMS: äSlow delivery of some silicon has delayed sensor production äYield problems and other difficulties with Honeywell SVX3D äInfancy failures of some chips l SUCCESSES: äOverall the projects are on track äMany problems solved äInstallation sometime in 2000 should be possible