V5 cluster search USB Rx USB Tx DSP Core DSP Controller Cluster FIFO ADC Data PC data

HIP core State Machine FIFO RD FIFO WR Register 1..N Line FIFO L0,C0 Ctrl DSP Channel Cluster list FIFO SM control Data outCluster list DATA L0, C0 DATA To USB From USB Raw/list data sel.

Mask for image processing Line delay P -2,-2 P -2,-1 P -2,0 P -2,1 P -2,2 DataIn P -1,-2 P -1,-1 P -1,0 P -1,1 P -1,2 P 0,-2 P 0,-1 P 0,0 P 0,1 P 0,2 P 1,-2 P 1,-1 P 1,0 P 1,1 P 1,2 P 2,-2 P 2,-1 P 2,0 P 2,1 P 2,2

Complete block diagram Search Matrix Matrix Data DataIn Clustering Channel Control logic L0 C0 Pedestal memory Gain Noise (Optional) Reconstructed image x Bad pixel mask 0 Matrix Data... Cluster validation Sub pixel (COG) Th Neig. 2x N fps >> n Cluster Matrix Size Charge Length Width Digital pixel Bad pixel List Divide by 2^n Seed Logic Th Seed

FPGA system DDR3  Controller DSP Ethernet FPGA Displayjtag ADCs

Control packge received by the FPGA system ID (4 bits)Type (2 bits)Size (10 bits) DATA (0) DATA (1)... Data (Size -1) ID refers to the submodule that the package is being sent. TYPE could be write register, read register, write data… Size is this package size, we want small for read/write register but big ones to download data such as the pedestal.

DSP DDR3 DSP Controller DSP Core Bias & Clock DSP Displayjtag ADCs

 Controller block diagram NiosIISG DMATSE core DDR3 ctrl PIO

1 channel for the whole frame Mask line0 line1 line2 line3 line4 MaskIn FIFOFIFO DataIn Seed logic DataOut channel Control logic L0 C0

Two channel system Mask line0 line1 line2 line3 line4 MaskIn FIFOFIFO DataIn Seed logic DataOut left channel Control logic L0 C0 Mask line0 line1 line2 line3 line4 MaskIn FIFOFIFO DataIn Seed logic DataOut right channel Control logic L0 C0 Shared data

Three or more channels Mask line0 line1 line2 line3 line4 MaskIn FIFOFIFO DataIn Seed logic DataOut left channel Control logic L0 C0 Mask line0 line1 line2 line3 line4 MaskIn FIFOFIFO DataIn Seed logic DataOut center channel 1.. n Control logic L0 C0 Shared data Mask line0 line1 line2 line3 line4 MaskIn FIFOFIFO DataIn Seed logic DataOut right channel Control logic L0 C0 Shared data