Electronic system level design Teacher : 蔡宗漢 Electronic system level Design Lab environment overview Speaker: 范辰碩 2012/10/231

Teacher : 蔡宗漢 Electronic system level design Outline  Overview of ESL design tool  Introduction of AndESLive 2012/10/232

Overview of ESL design tool 2012/10/233

Teacher : 蔡宗漢 Electronic system level design ESL design tool 2012/10/234  In this course, we adopt two ESL design tool in the lab.  CoWare  It provide a virtual platform to achieve a ESL design  use various component to combine a system level design, such as ARM CPU core, AHB, APB, user define IP and etc.  AndESLive  To provide a virtual platform to achieve a SoC/ESL design  Include Andes CPU core and various soft IP component

Introduction of AndESLive 2012/10/235

Teacher : 蔡宗漢 Electronic system level design Virtual SoC and software design flow 2012/10/236

Teacher : 蔡宗漢 Electronic system level design What is Virtual Platform? “ It is a system-level simulation model that characterizes real system behavior. It operates at the level of processor instructions, function calls, memory accesses and data packet transfers, etc, as opposed to the bit-accurate, nanosecond-accurate logic transitions of a register transfer level (RTL) model.” Andes Development Platform Andes Virtual Platform 2012/10/237

Electronic system level design Teacher : 蔡宗漢 Integrated Development Environment S/W Development with Andes Tools SW Developer Desktop (AndeSight TM ) DEVICE SOFTWARE STACK VEP (AndESLive TM ) Operating Systems BSP/Device Drivers Middleware Applications Operating Systems BSP/Device Drivers Middleware Applications Editor Compiler Debugger Assembler Program Builder Profiler SOC Builder Other plug-in tools AndESLive TM /API AndeSoft TM Virtual I/O Connectivity 2012/10/238

Teacher : 蔡宗漢 Electronic system level design AndESLive™ VEP Environment  Cycle-accurate CPU simulation model  Speed: 30 MIPS  Pre-built IP models  Generic: dram controller, bus controller, DMA, GPIO, etc.  Controllers for LCD, MAC, USB, etc.  Virtual IO service to speed up simulation for non-focused modules  Customer’s IP models  Thru C++ interface  SoC Builder  Construct SoC thru GUI drag-and-drop  List memory/interrupt mapping for SW engineers 2012/10/239