Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 3: September 12, 2011 Transistor Introduction (first order)

Today First order model There are always Rs and Cs Penn ESE370 Fall DeHon 2

Last Time Quasi-Static – inputs transition, circuit responds, and settles –Dynamic transition to roughly static states DC/Steady-State –Ignore the capacitors Zeroth-order allows us to reason (mostly) at logic level about steady-state functionality of typical gate circuits Penn ESE370 Fall DeHon 3

Zero-th Order MOSFET Ideal Switch Vgs > Vth  conducts Vgs < Vth  does not conduct Vth – threshold voltage Gate draws no current from input –Loads input capacitively Penn ESE370 Fall DeHon 4

Zero-th Order MOSFET Penn ESE370 Fall DeHon 5 I DS

First Order Model Switch –Loads gate input capacitively C g –Has finite drive strength R on Penn ESE370 Fall DeHon 6

Gate Output Assume this is equivalent circuit for gate output state Penn ESE370 Fall DeHon 7

Gate Output Load What is Vout if gate is unloaded? Penn ESE370 Fall DeHon 8

Gate Output Load What happens to Vout when add a load? Penn ESE370 Fall DeHon 9

Resistive Load What happens when load is resistance? Penn ESE370 Fall DeHon 10

Resistive Load If loaded resistively, and resistive load is too strong (resistance too low) Cause output voltage to drop Penn ESE370 Fall DeHon 11

Capacitive Load What happens when load is capacitance? Penn ESE370 Fall DeHon 12

Capacitive Load Capacitive load does not change the steady-state output voltage Will effect the delay (settling time) Penn ESE370 Fall DeHon 13

First Order Model Switch –Loads gate input capacitively Draw no current Does not impact steady-state voltage Impacts Delay –Has finite drive strength Could form voltage divider with resistive load Impacts Delay Penn ESE370 Fall DeHon 14

First Order Model (vs. Vds) Penn ESE370 Fall DeHon 15

First Order Model (vs. Vgs) Penn ESE370 Fall DeHon 16

Refine to First Order Penn ESE370 Fall DeHon 17

Zero-th Order Tells us how switches set (Vin=0) Penn ESE370 Fall DeHon 18 How are switches set in this case?

Zero-th Order Tells us how switches set (Vin=0) Penn ESE370 Fall DeHon 19 V2=Vdd Vout=0

Zero-th Order Tells us how switches set (Vin=0) Penn ESE370 Fall DeHon 20 V2=Vdd Vout=0 Vdd Gnd

Zero-th Order Tells us how switches set (Vin=0) Leaves an RC Circuit we can analyze Penn ESE370 Fall DeHon 21 Vdd Gnd ESE215 problem

Zero-th Order Tells us how switches set (Vin=0) Look at middle stage (V2) Penn ESE370 Fall DeHon 22 What is equivalent circuit of load at V2? Vdd Gnd

Zero-th Order Tells us how switches set (Vin=0) Look at middle stage (V2) Penn ESE370 Fall DeHon 23 What is equivalent ouptut circuit for first pair of transistors driving V2? Vdd Gnd

Zero-th Order Tells us how switches set (Vin=0) Look at middle stage (V2) Penn ESE370 Fall DeHon 24 What is relevant circuit? Gnd Vdd

Zero-th Order Tells us how switches set (Vin=0) Look at middle stage (V2) Penn ESE370 Fall DeHon 25 What is relevant circuit? Gnd Vdd

Zero-th Order Tells us how switches set (Vin=0) Look at middle stage (V2) Penn ESE370 Fall DeHon 26 Gnd Vdd What is delay of this stage? (charging V2 when Vin switch Vdd  0)

What more does first-order model tell us? Delay Quastistatic behavior Voltage settling with resistive loads –At least some basis for reasoning Penn ESE370 Fall DeHon 27

What is this leaving out? Penn ESE370 Fall DeHon 28

What is this leaving out? Penn ESE370 Fall DeHon 29

What leaving out? What happens at intermediate voltages –Not rail-to-rail Details of dynamics, including… –Input not transition as step –Intermediate drive strengths change with Vgs Isn’t really 0 current below threshold Penn ESE370 Fall DeHon 30

Engineering Control Vth – process engineer Drive strength (R on )– circuit engineer control with sizing transistors Supply voltages (Vdd) –range set by process –detail use by circuit design Penn ESE370 Fall DeHon 31

Engineering Control: Threshold Penn ESE370 Fall DeHon 32

Engineering Control: Drive Strength Penn ESE370 Fall DeHon 33

Rs and Cs Penn ESE370 Fall DeHon 34

Wire Capacitance Penn ESE370 Fall DeHon 35

Wire Capacitance Penn ESE370 Fall DeHon 36

Wire Resistance Penn ESE370 Fall DeHon 37

Wire Resistance Penn ESE370 Fall DeHon 38

Wire Resistance Sanity check –Wire twice as long = resistors in series –Wire twice as wide = resistors in parallel Penn ESE370 Fall DeHon 39

There are always Rs and Cs Every wire (connection) has resistance Every wire has capacitance (Every wire has inductance) Modeling vs. discrete components Dominant effects –Rbig + Rsmall ≈ Rbig (Rwire << Ron)? –Cbig || Csmall ≈ Cbig (Cwire<<Cg) ? Penn ESE370 Fall DeHon 40

Admin TA: Paul Gurniak – pgurniak seas –Office Hours: W3-4pm, R1:30-2:30pm Ketterer André office hours: T4:00pm Lecture Wednesday: building gates –Reading Lab on Friday –Homework due, bring USB drive Penn ESE370 Fall DeHon 41

Penn ESE370 Fall DeHon 42 MOSFET

Big Ideas MOSFET Transistor as switch Purpose-driven simplified modeling –Aid reasoning, sanity check, simplify design Analysis methodology –zero-th order to understand switch state (logic) –First-order to get equivalent RC circuit (delay) New perspective on Rs and Cs Penn ESE370 Fall DeHon 43