Slide 1 IRAM and ISTORE Projects Aaron Brown, Jim Beck, Rich Fromm, Joe Gebis, Kimberly Keeton, Christoforos Kozyrakis, David Martin, Morley Mao, Rich Martin, David Oppenheimer, Steve Pope, Randi Thomas, Noah Trefault, John Kubiatowicz, Kathy Yelick, and David Patterson DIS DARPA Visit

Slide 2 + Vector Registers x ÷ Load/Store Vector 4 x 64 or 8 x 32 or 16 x 16 4 x 64 Queue Instruction V-IRAM1: 0.18 µm, Fast Logic, 200 MHz 1.6 GFLOPS(64b)/6.4 GOPS(16b)/16-32MB Memory Crossbar Switch 16K I cache 16K D cache 2-way Superscalar Processor I/O Serial I/O

Slide 3 IRAM in the News IRAM mentioned in N.Y.Times, July 19, 1999 –“A Renaissance In Computer Science; Chip Designers Search for Life After Silicon,” By John Markoff “... Mr. Patterson, the RISC pioneer, has now embarked on a new design approach, known as intelligent RAM, or IRAM, that has generated great interest among consumer electronics companies.... Mr. Patterson and his Berkeley colleagues have noted that the largest performance constraint in computer systems today is the mismatch in speed between the microprocessor and the slower memory chips. The Berkeley researchers predict that in the next decade processors and memory will be merged in a single chip. “The IRAM chips would embed computer processors in vast seas of memory transistors. Instead of stressing pure processor speed, these new chips would place the emphasis on avoiding bottlenecks that slow the data traffic inside a processor. Such an approach would be especially attractive to makers of memory chips -- companies eager to find new ways to distinguish themselves in what is now a commodity market.... For example, the Sony Corporation's Emotion Engine chip,... for the coming Sony Playstation II game console, blends memory and processor logic as a way to create faster, more vivid on-screen game action.”

Slide 4 Sony Playstation 2000 Emotion Engine: 6.2 GFLOPS, 75 million polygons per second (Microprocessor Report, 13:5) –MIPS core + vector coprocessor + graphics/DRAM –Claim: Toy Story realism brought to games!

Slide 5 IRAM Update IBM to supply embedded DRAM/Logic (99%) –DRAM macro added to 0.18 micron logic process –First standard customer chips accepted 4/1/00 –(IBM uses “Palm Pilot X” in technology announcement) Sandcraft to Supply Scalar Core –64-bit, dual scalar MIPS embedded processor, 16 KB I and D caches, TLB, FPU –Will copy TLB, FPU design in vector unit –Sandcraft to port processor to IBM process VIRAM test chip tapped out to LG Semicon –delays due to strike, Korean economy; merger –Tape out 11/98; 2 rounds of bad wafers; last batch in October

Slide 6 IRAM Update Instruction Set Architecture Manual and Simulator complete –Revised DSP support –Revised Arithmetic Exceptions Detailed Performance simulator in use Continuting to Write Verilog of control now Design of multiplier, register file done; layout underway Retargeting Cray vectorizing compilers to VIRAM

Slide 7 Intelligent Storage Project Goals ISTORE: a hardware/software architecture for building scaleable, available, self-maintaining storage –Designed for data-intensive apps: e.g., –data bases, out-of-core FFT –Thus need S.A.M. benchmarks: Scalability, Availability, Maintainability Self-maintenance: no administrators to configure, monitor, or tune system –An introspective system: it monitors itself and acts on its observations

Slide ISTORE IBM MicroDrive 1.7”x1.4”x0.2” –1999: 340 MB, 5400 RPM, 5 MB/s, 15 ms seek –2006 MD: 9 GB, 50 MB/s ( ” disk: 1TB, 200 MB/s) ISTORE node –MicroDrive + System On a Chip (CPU, memory, redundant NI, diagnostic proc.) Crossbar switches growing by Moore’s Law –16 x 16 in 1999  64 x 64 in 2005 ISTORE rack (19” x 33” x 84”) –1 tray (3” high)  16 x 32  512 ISTORE nodes –20 trays+switches+UPS  10,240 ISTORE nodes(!)

Slide 9 ISTORE Update ISTORE-0: 6 PCs in lab connected via Ethernet Switch ISTORE-1: 64 nodes “PC”+low profile disk+ disagnoistic processor in half-height disk cannister, plus redundant swtiches, power supplies –Under construction, to be delivered in October Agreement with Compaq/DEC SRC to get sources of Petal System (a data block server) to act as software layer for ISTORE Met with Microsoft about databases; will meet with IBM about databases in the future

Slide 10 ISTORE in the News ISTORE ideas in Computer, August, 1999 –“ The Future of Systems Research,” By John Hennessy After 20 years in academia and the Silicon Valley, the new Provost of Stanford University calls for a shift in focus for systems research. Performance-- long the centerpiece--needs to share the spotlight with availability, maintainability, and other qualities. Although performance increases over the past 15 years have been truly amazing, it will be hard to continue these trends by sticking to the basically evolutionary path that the research community is currently on. The author advocates a more evolutionary approach to systems problems and thinks the approach needs to be more integrated. Researchers need to think about hardware and software as a continuum, not as separate parts. He sees society on the threshold of a "Post PC" era, in which computing is ubiquitous, and everyone will use information services and everyday utilities. When everyone starts using these systems, guess what? They expect them to work and to be easy to use. So this era will drive system design toward greater availability, maintainability, and scalability, which will require a real refocusing of current research directions.