July 17, 2013 CERN T. Flick University of Wuppertal

Pixel Opto-Electronics and this Review The Pixel project builds a 4 th pixel layer (the IBL) ready for installation in LS1 (2013/14) The front-end electronics has been developed newly and the off- detector electronics needs to be adapted to this. 14 IBL staves with 32 chips/stave will be installed Each stave is read out on both ends; each half-stave (i.e. 16 chips) is read out through one optoboard (electrical to optical transition) to the BOC/ROD system in USA15 This review will focus on the off-detector readout cards: Readout Driver (ROD) and Back of Crate card (BOC) The key building blocks of the new off-detector readout electronics for the IBL and its functionalities are o The ReadOut Driver (ROD): Control part of the readout. Steering of calibration and data taking and event building capabilities. o The Back Of Crate card (BOC): Timing capabilities and optical interface towards detector and readout system. Data en- and decoding functionalities IBL ROD/BOC PRR Introduction2 IBL= Insertable B-Layer

New developments for IBL The IBL will be installed closer to the beam-pipe. o Higher occupancy in the modules o Chance to provide a more accurate space point To handle the higher occupancy and provide a readout bandwidth coping with the amount of data, a new readout chip has been developed Pixel dimensions have been reduced with this as well Improvements in terms of readout: o Higher readout bandwidth (160 Mb/s per chip) o Balanced signal (8b/10b encoded) To handle the new electronics also off-detector wise a new card pair (ROD/BOC) has been developed o 16 output links at 40 Mb/s BPM encoded signal (same as for Pixel) o 32 input links at 160 Mb/s o 4 S-Links per pair to drive the data out o Faster calibration link by using Gb Ethernet instead of the VME bus for data transfer IBL ROD/BOC PRR Introduction3

Insertable B-Layer (IBL) The 4 th Pixel layer (IBL) is currently under construction 14 new staves, new FE chips, new readout protocol IBL ROD/BOC PRR Introduction

Readout Scheme Overview IBL ROD/BOC PRR Introduction5 ……………. VME readout crate 16 card pairs (ROD/BOC) VME readout crate 16 card pairs (ROD/BOC) Detector Module Optoboard (housed in Optobox) Optoboard (housed in Optobox) S-Link RX TX Optical BPM Optical 8b/10b ROS Detector Module Halfstave Optical 8b/10b Optical BPM Electrical Counting Room Counting Room ID end- plate ID end- plate Detector Volume Detector Volume 80m 5-7m Optoboard (housed in Optobox) Optoboard (housed in Optobox)

ATLAS IBL Readout Structure IBL ROD/BOC PRR Introduction6 16 modules VME crate 2 FE-I4 2 optoboards DORIC VDC BOC ROD TIM SBC S-Link RX TX Timin g Control & data handling Control & data handling Control and steering Event building Optical BPM Optical 8b10b ROS EthernetEthernet EthernetEthernet IBL stave IBL optobox on ID endplate opticallyelectrically

On-detector: Optoboard On-detector optical interface 2 VSCEL arrays, 1 PiN diode array, 8 channels utilized per array. Will run at 40Mb/s receive and 160 Mb/s transmit bandwidth DORIC (digital optical receiver IC) for decoding clock and data for the modules VDC (VCSEL Driver Chip) for driving the lasers DORIC and VDC are the same as used already on the Pixel detector optoboards IBL ROD/BOC PRR Introduction7 KK Gan, Shane Smith (Ohio) VCSEL PiN Diode

Off-detector Plugins & Fibres IBL will use new off-detector optical plugins situated on the BOC Commercial SNAP12 plugins have been chosen New additional fibres for IBL will be installed to connect the off- end on-detector parts. Again 8 channels will be used per fibre tube IBL ROD/BOC PRR Introduction8 Alberto Cervelli (Bern)

IBL Readout Driver IBL ROD/BOC PRR Introduction 9 Control card o Steering of detector Configuration Commands o Detector calibration by steering the calibration scans o Physics data taking Trigger sending, event building o Histogramming for calibration and monitoring Master FPGA: o Control data generation o Run control (calibration scans and data taking) Slave FPGAs: o Data interface to and from Back of Crate Card o Data preparation and histrogramming GbE Master FPGA Master FPGA Slave FPGA Slave FPGA ROD RevC

IBL Back of Crate Card Timing interface o Receive clock from TIM o Distribute the clock to detector components and ROD Optical interface to/from detector and readout buffers o SNAP12 plugins (Tx / Rx) o S-Link plugins (QSFP) Data en-/decoding for detector communication o BPM encoding towards the detector o 8b/10b decoding for the detector data to hand over to the ROD Monitoring functionalities for detector data IBL ROD/BOC PRR Introduction10 GbE QSFP Rx/Tx Plugins Control FPGA Main FPGA BOC RevC

IBL ROD/BOC PRR Introduction Production & Installation Schedule The IBL is included into the overall Pixel schedule for 2013/14 and in consequence into the ATLAS LS1 schedule Before installation the cards need to serve the full IBL test in SR1 Systemtest in SR1 is under construction and will serve as test platform also for the readout cards Installation itemsExpected timecomment Card productionFrom July 2013Prototypes ready in revC SystemtestingJune Set-up phase ongoing IBL full testNovember 2013Have all the readout and services ready in SR1 Installation of off-detector parts for readout and power Jan/Feb 2014Whenever they can be taken from final SR1 tests Cabling of detector in pitMar 2014After IBL installation Commissioning tests and sign-off for closure April-June 2014Sequence of warm/cold test Ready for closureEnd June 2014

Documentation The review Master Document is under: ATL-SYS-ER-0027ATL-SYS-ER-0027 It holds the drawing files as sub-docs. Further documentation on the agenda page: ROD o IBL ROD revC Manual & Appendix o IBL ROD tests document o IBL ROD production process document o IBL ROD current firmware status document BOC o IBL BOC design and firmware manual o Production test plans Additional documents o FE-I4B Manual o IBL PPC scans document IBL ROD/BOC PRR Introduction12

The Goal for the ROD/BOC Review Subject of this review is the construction of IBL ROD & BOC cards, which form the off-detector readout part of the IBL. This includes o Production and qualification of Read Out Drivers o Production and qualification of Back of Crate Cards o Plans for system commissioning o Installation schedule We also present the plans of using the cards for upgrading Layer 1 and Layer 2 of the current Pixel Detector to overcome bandwidth limitations due to increased luminosity until IBL ROD/BOC PRR13

Agenda Review presentations: o Introduction and overall schedule o ROD technical items o BOC technical items o Testing done and planned Indico page: o confId= confId= EDMS page: o Would be delighted to have initial feedback and draft report shortly after the review. Many thanks to our reviewers for their time and effort! IBL ROD/BOC PRR14