Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory Clocks Data FEDv1 Final Firmware Subtasks Serial Comms VME LINK VME Bus VME SystemACE System ACE Clocks EPROM EPROM TTCrx QDR Write QDRs QDR Read Serial Comms Headers TTC chanA VME LinkRegs S-LINK S-LINK Clocks Data Serial Comms Scope Mode Header Mode FIFOs Input Regs Serial Comms Scope Mode Header Mode Output Input Regs Opto Rx DAC Opto Rx DAC DELAY FPGA x 3 x 8 FE FPGA x 8 BE FPGA VME FPGA ADC Under Simulation Under Test on FED FEDv2 Controls Data Readout Control Throttle TCS Input ClusterMode Ed Saeed Ivan Ed Ed, John Saeed, Ivan Chan B I2C Temp “Working” on FED External Devices Temp 15th May 2003 To be Implemented

Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory Clocks Data FEDv1 Final Firmware Subtasks Serial Comms VME LINK VME Bus VME SystemACE System ACE Clocks EPROM EPROM TTCrx QDR Write QDRs QDR Read Serial Comms Headers TTC chanA VME LinkRegs S-LINK S-LINK Clocks Data Serial Comms Scope Mode Header Mode FIFOs Input Regs Serial Comms Scope Mode Header Mode Output Input Regs Opto Rx DAC Opto Rx DAC DELAY FPGA x 3 x 8 FE FPGA x 8 BE FPGA VME FPGA ADC Under Simulation Under Test on FED FEDv2 Controls Data Readout Control Throttle TCS Input ClusterMode Ed Saeed Ivan Ed Ed, John Saeed, Ivan Chan B I2C Temp “Working” on FED External Devices Temp 11th June 2003 To be Implemented

Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory Clocks Data FEDv1 Final Firmware Subtasks Serial Comms VME LINK VME Bus VME SystemACE System ACE Clocks EPROM EPROM TTCrx QDR Write QDRs QDR Read Serial Comms Headers TTC chanA VME LinkRegs S-LINK S-LINK Clocks Data Serial Comms Scope Mode Header Mode FIFOs Input Regs Serial Comms Scope Mode Header Mode Output Input Regs Opto Rx DAC Opto Rx DAC DELAY FPGA x 3 x 8 FE FPGA x 8 BE FPGA VME FPGA ADC Under Simulation Under Test on FED FEDv2 Controls Data Readout Control Throttle TCS Input ClusterMode Ed Saeed Ivan Ed Ed, John Saeed, Ivan Chan B I2C Temp “Working” on FED External Devices Temp 26th June 2003 To be Implemented

Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory Clocks Data FEDv1 Final Firmware Subtasks Serial Comms VME LINK VME Bus VME SystemACE System ACE Clocks EPROM EPROM TTCrx QDR Write QDRs QDR Read Serial Comms Headers TTC chanA VME LinkRegs S-LINK S-LINK Clocks Data Serial Comms Scope Mode Header Mode FIFOs Input Regs Serial Comms Scope Mode Header Mode Output Input Regs Opto Rx DAC Opto Rx DAC DELAY FPGA x 3 x 8 FE FPGA x 8 BE FPGA VME FPGA ADC Under Simulation Under Test on FED FEDv2 Controls Data Readout Control Throttle TCS Input ClusterMode Ed Saeed Ivan Ed Ed, John Saeed, Ivan Chan B I2C Temp “Working” on FED External Devices Temp 23rd July 2003 To be Implemented

Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory Clocks Data FEDv1 Final Firmware Subtasks Serial Comms VME LINK VME Bus VME SystemACE System ACE Clocks EPROM EPROM TTCrx QDR Write QDRs QDR Read Serial Comms Headers TTC chanA VME LinkRegs S-LINK S-LINK Clocks Data Serial Comms Scope Mode Header Mode FIFOs Input Regs Serial Comms Scope Mode Header Mode Output Input Regs Opto Rx DAC Opto Rx DAC DELAY FPGA x 3 x 8 FE FPGA x 8 BE FPGA VME FPGA ADC Under Simulation Under Test on FED FEDv2 Controls Data Readout Control Throttle TCS Input ClusterMode Ed Saeed Ivan Ed Ed, John Saeed, Ivan Chan B I2C Temp “Working” on FED External Devices Temp 22nd August 2003 To be Implemented

Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory Clocks Data FEDv1 Final Firmware Subtasks Serial Comms VME LINK VME Bus VME System ACE System ACE EPROM TTCrx QDR Write QDRs QDR Read Serial Comms Headers TTC chanA VME LinkRegs S-LINK Clocks Data Serial Comms Scope Mode Header Mode FIFOs Input Regs Serial Comms Scope Mode Header Mode Output Input Regs Opto Rx DAC Opto Rx DAC DELAY FPGA x 3 x 8 FE FPGA x 8 BE FPGA VME FPGA ADC Under Simulation Under Test on FED Controls Data Readout Control Throttle TCS Input Cluster Mode Ed->Saeed Saeed Saeed Ed->Saeed Ed, John Saeed, Ivan Chan B I2C “Working” on FED External Devices Temp 4th November 2003 To be Implemented Spy Clocks FEDv2