HB LED Pulser Boards By Michael Miller The University of Iowa.

Slides:

Advertisements

Similar presentations

18 Bit ADC Status Collaboration meeting May 18, 2007.

Advertisements

HCAL RBX PRR Overview Jim Freeman RBX PRR March 1-2, 2001.

SKIROC New generation readout chip for ECAL M. Bouchel, J. Fleury, C. de La Taille, G. Martin-Chassard, L. Raux, IN2P3/LAL Orsay J. Lecoq, G. Bohner S.

4-channel ASIC Tests Michael Baumer, Jean-Francois Genat, Sam Meehan, Eric Oberla August 26 th 2009.

1 Project supervised by: Dr Michael Gandelsman Project performed by: Roman Paleria, Avi Yona 12/5/2003 Multi-channel Data Acquisition System Mid-Term Presentation.

ANITA Calibration System Jason Link University of Hawaii ANITA Collaboration Meeting at UCI 4/7/05 – 4/9/05.

Team LIT Scott Butler Kristin Haeusler Michael Hatt Brock Smith.

B wheel Board Gain Differences Mitch Newcomer May 5, 2005.

E. Hazen, Boston University BU Meeting, Apr. 6, 2001 Front-end Readout of the CMS Hadronic Forward Calorimeter (HF) Conceptual Design (Summary) by Eric.

TEST YOUR BRAIN! Components.

Status of LAV FEE electronics G. Corradi, C. Paglia, D. Tagnani & M. Raggi, T. Spadaro, P. Valente.

Various Topics Related to FEB Liang Han, Ge Jin University of Science and Technology of China Dec.21,2013.

MICROCONTROLLER BASED FIRE FIGHTING ROBOT. ABSTRACT The object of this project is  IN OUR PROJECT WE DESIGNED A PROTOTYPE TO DETECT FIRE AND EXTINGUISH.

Feb 20, 2009 CALICE meeting, Daegu, Korea QRL in Magnetic Field 1 QRLed Driver in Magnetic Field Jaroslav Zalesak Institute of Physics of the ASCR, Prague.

Iowa LED system for CMS HCAL By M. Miller Y. Onel University of Iowa, Iowa City, IA CMS Meeting, CERN December 1-8, 2001.

1 Applied Control Systems Technology. 2 Pin configuration Applied Control Systems.

Second generation Front-end chip for H-Cal SiPM readout : SPIROC DESY Hamburg – le 13 février 2007 M. Bouchel, F. Dulucq, J. Fleury, C. de La Taille, G.

Gunther Haller SiD LOI Meeting March 2, LOI Content: Electronics and DAQ Gunther Haller Research Engineering Group.

U.B. Presentation October Bernard COURTY L.P.C.C. College de France - Paris.

Ondřej Svoboda for the ECAL group HADES collaboration meeting XXV, 19 – 23 November 2012 GSI.

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 1 Development of fast electronics for the GRAPES-3 experiment at Ooty K.C. RAVINDRAN On Behalf of GRAPES-3 Collaboration.

Figure 1: ICD Single Channel Block Diagram Schematic PMT High Voltage Supply (see Figure 4 & 4a) LED Pulser PMT Calibration (see Figure 6) ICD Scintillator.

Beam phase and intensity measurement Grzegorz Kasprowicz Richard Jacobsson.

Students:Alexander Kinko Roni Lavi Instructor:Inna Rivkin Duration:2 Semesters Midterm Presentation Part 1 - Spring 2008 Midterm Presentation Part 1 -

LNL 1 SLOW CONTROLS FOR CMS DRIFT TUBE CHAMBERS M. Bellato, L. Castellani INFN Sezione di Padova.

September 8-14, th Workshop on Electronics for LHC1 Channel Control ASIC for the CMS Hadron Calorimeter Front End Readout Module Ray Yarema, Alan.

Light Calibration System (LCS) Temperature & Voltage Dependence Option 2: Optical system Option 2: LED driver Calibration of the Hadronic Calorimeter Prototype.

Munich, 18 Oct 2006J. Cvach, annual JRA31 JRA3 Institute of Physics ASCR Prague 1.ECAL, VFCAL (V. Vrba) 2.HCAL (J. Cvach) 3.Exchange in NA2 (travels 8.5.

LOGIC GATES. Electronic digital circuits are also called logic circuits because with the proper input, they establish logical manipulation paths. Each.

S. Los CMS Upgrade Workshop, October 28, 2009, FNAL 1 SiPM Signal Shaping Sergey Los FNAL/CMS/HCAL.

8114A Overview. 8114A Overview 10-Feb-04 Page A Overview 1) Specifications and Applications 2) Operational Overview 3) Block Diagram.

Acquisition Crate Design BI Technical Board 26 August 2011 Beam Loss Monitoring Section William Vigano’ 26 August

CALIBRATION OF TEVATRON IONIZATION PROFILE MONITOR (IPM) FRONT END (FE) MODULES Moronkeji Bandele Physics and Engineering Department Benedict College,

March 9, 2005 HBD CDR Review 1 HBD Electronics Preamp/cable driver on the detector. –Specification –Schematics –Test result Rest of the electronics chain.

Update on final LAV front-end M. Raggi, T. Spadaro, P. Valente & G. Corradi, C. Paglia, D. Tagnani.

Towards a final design of LAV front-end M. Raggi, T. Spadaro, P. Valente & G. Corradi, C. Paglia, D. Tagnani.

7/28/2003DC/EC Review Aerogel Read out Electronics K. Ozawa, N. Kurihara, M. Inaba, H. Masui T. Sakaguchi, T. Matsumoto.

ASIC Activities for the PANDA GSI Peter Wieczorek.

Main HCAL, JUL1,2008Ivo Polak, IP_ASCR, Prague1 Calibration system with optical fibers HCAL main meeting, DESY.

Plans and Progress on the FPGA+ADC Card Pack Chris Tully Princeton University Upgrade Workshop, Fermilab October 28, 2009.

FEE card validation M. Raggi, T. Spadaro. The problem Validate FEE production – threshold determination at < 1mV accuracy – comparator time effects: Overdrive.

QIE10 development Nov. 7, 2011: The first full-chip prototype was submitted to MOSIS. Output is 2-bit exponent (four ranges) and 6-bit mantissa (non-linear.

SKIROC ADC measurements and cyclic ADC LPC Clermont-Ferrand Laurent ROYER, Samuel MANEN Calice/Eudet electronic meeting Orsay June.

8133A Overview. 8133A Overview 10-Feb04 Page A Overview 1) Specifications and Applications 2) Operational Overview 3) Block Diagram.

AHCAL Integration. Status and Outlook Mathias Reinecke for the AHCAL developers CALICE week Lyon IPNL, Sept. 16th – 18th, 2009.

DCS meeting - CERN June 17, 2002V.Kouchpil SDD DCS status Low Voltage system End-ladder ASIC High Voltage system Cooling system Schedule.

1 Timing of the calorimeter monitoring signals 1.Introduction 2.LED trigger signal timing * propagation delay of the broadcast calibration command * calibration.

Readout controller Block Diagram S. Hansen - CD-1 Lehman Review1 VXO Ø Det Links to 24 SiPM Front End Boards Clock Event Data USB ARM uC A D Rd Wrt 100Mbit.

AHCAL Electronics. Status of Integration Mathias Reinecke for the DESY AHCAL developers AHCAL main and analysis meeting Hamburg, July 16th and 17th, 2009.

Week 22: Schematic Week 23-Week 27: Routing Gerber files have been available since 9th July 1st prototype: – PCB manufacturer: supervised by KIT – Cabling:

HE FEE Boards production status 26 th May 2016 Mandakini Patil 1.

C osmic R Ay T elescope for the E ffects of R adiation 27 June 2005 Digital Engineering Digital Sub-System Bob Goeke.

SKIROC status Calice meeting – Kobe – 10/05/2007.

MADEIRA Valencia report V. Stankova, C. Lacasta, V. Linhart Ljubljana meeting February 2009.

Configuration and local monitoring

JRA3 Institute of Physics ASCR Prague

on behalf of the AGH and UJ PANDA groups

ECAL Front-end development

Baby MIND Collaboration Meeting #2

HF Test station at P5 A.Mestvirishvili.

96-channel, 10-bit, 20 MSPS ADC board with Gb Ethernet optical output

A New Clock Distribution/Topology Processor Module for KOTO (CDT)

Synchronization Policy: HCAL will follow ECAL as much as possible

Multi-Pixel Photon Counter Readout Board

Felix Sefkow CALICE/EUDET electronics meeting CERN, July 12, 2007

STATUS OF SKIROC and ECAL FE PCB

Jean-Francois Genat, Sam Meehan, Eric Oberla August 26th 2009

M. Krivda for the ALICE trigger project, University of Birmingham, UK

Presented by T. Suomijärvi

The Ohio State University USCMS EMU Meeting, FNAL, Oct. 29, 2004

Presentation transcript:

HB LED Pulser Boards By Michael Miller The University of Iowa

HB LED Pulser Boards HB Pulser board has the same mechanical format as the HB QIE Card. Pulser is controlled through the CCA (channel control) ASIC via the RBX Serial Bus. There are 2 semi independent pulsers on the board. Output amplitude is between 1.4 & 5.2 V. LED output light profile is similar to the signal from the megatiles. Board provides 5V biasing for up to 6 independent PIN diodes. For the pulse amplitude the “Pedestal DAC” outputs are used. Vout=5.2V – N*15.3mV where N is the 8 bit Pedestal DAC setting. Timing for the two LED pulsers is derived from the “Test Pulse” CCA output. This 25 ns signal can be masked for channels A and B independently and timed to any bunch crossing of the LHC orbit. Two external inputs facilitate pulser testing and make it possible to work without TTC infrastructure. There were several minor changes after the first prototype: 2 extra CCA outputs are used to allow individual triggering for Pulser A and Pulser B. Maximum output DAC voltage was changed from 2.55V to 3.9V to increase the dynamic range of the LED signal.

LED Pulser Board Block Diagram

Pulser Electrical Diagram

LED Connection

HB LED Pulser Board Prototype

HB LED Pulser Board Prototype output signal integral profile at different amplitudes

LED Pulser Board prototype output signal dynamic range.

HB LED Pulser Boards Production Design, manufacture, quality control and delivery done by The University of Iowa. 30 LED Pulser Boards delivered to FNAL ASAP, on August LED Pulser Boards were tested at the University of Iowa and delivered to FNAL in Sept The Pulser Boards are o.k. and give enough signal.

HB LED Pulser Boards Production