Parallel Routing for FPGAs based on the operator formulation Yehdhih Ould Mohamed Moctar & Philip Brisk Department of Computer Science & Engineering University of California Riverside Speculation based approach for parallelizing an FPGA router Design Automation Conference (DAC 2014) San Francisco, CA, USA, June 1-5, 2014

Motivation Runtime of circuit design is dominated by P&R Maze Expansion consumes over 65% of Runtime Large number of non-conflicting operations executed at each iteration FPGA adaptation is slowed by CAD tools. Placement and routing dominates runtime of CAD for FPGAs The router spend nearly two thirds of its time exploring nodes of the RRG If we can speculate about the nature of the operation being performed on RRG nodes, we can identify many non-conflicting operations at each iteration

Contribution Application of Speculative Parallelism to FPGA routing Use of non-blocking priority queues for the Maze Expansion Implementation of the parallel router in VPR

FPGA Routing Find a physical path for every signal in the circuit Disjoint-path problem; NP-complete S To configure the programmable switches of the routing fabric to connect the logic blocks and the I/O pads of the circuit Technology variant of the well-known disjoint paths problem in Graph theory One of Carp’s 21 Pathfinder allows negotiation among signals that share the routing resources. T1 T2 Pathfinder: Negotiation-based algorithm

Routing Resource Graph (RRG) 2-LUT in1 in2 out wire1 wire2 wire3 wire4 sink out wire4 wire2 in2 in1 wire1 wire3 Large data structure representing the routing resources of the FPGA, pins and wires become nodes and switches become edges RRG represents the routing resources of the FPGA 5

Serial Pathfinder We Parallelize the Maze Expansion Triple nested loop, Global router establish the negotiation criteria, Signal router control negotiation among signals, and Maze router finds routes for individual nets Priority Queue driven diercted BFS on the RRG We Parallelize the Maze Expansion

Maze Expansion Operation PQ contains nodes that have not been fully explored

Galois Software framework for parallelizing irregular algorithms Employ speculation based approach to parallelism Operator formulation of algorithms Data-centric view of parallelism (Amorphous data parallelism) Works better on algorithms whose behavior is not known until runtime sparse graphs Parallel program = Operator + Schedule + Parallel data structure

Operator formulation of algorithms Computation at active element Activity: application of operator to active element Amorphous data-parallelism Multiple active nodes can be processed in parallel subject to neighborhood and ordering constraints : active node : neighborhood Parallel program = Operator + Schedule + Parallel data structure 9

Maze Expansion in Galois Each thread speculatively explore potential candidate nodes in the RRG Galois offers Low mis-speculation/rollback cost Threads speculatively explore the node of RRG Each Thread has a local Priority Queue

Benchmarks We selected 10 of the largest IWLS benchmarks. We target 65nm CMOS (BPTM)

Maze Router Speedup Achieved up-to 5.5x speedup (Using 8 threads) Steady Scalability up to 8 threads

Maze Router – Configuration Options (Normalized Speedup) STM PQ + Iteration Coalescing achieved 5.46x speedup

Maze Router - Critical Path Delay (CPD) # of Threads has no impact on Critical Path Delay (CPD) Parallel implementation achieved better CPD than VPR

Conclusion & Future Work Speculative parallelism can be good choice for parallel CAD algorithms Achieved Near-linear speedup (up to 5.5x) over Serial FPGA Router. Future work includes applying this speculative model to parallelize Placement.