Digital System Clocking: High-Performance and Low-Power Aspects Vojin G. Oklobdzija, Vladimir M. Stojanovic, Dejan M. Markovic, Nikola M. Nedovic Wiley-Interscience.

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Digital System Clocking: High-Performance and Low-Power Aspects Vojin G. Oklobdzija, Vladimir M. Stojanovic, Dejan M. Markovic, Nikola M. Nedovic Wiley-Interscience.

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Presentation transcript:

Digital System Clocking: High-Performance and Low-Power Aspects Vojin G. Oklobdzija, Vladimir M. Stojanovic, Dejan M. Markovic, Nikola M. Nedovic Wiley-Interscience and IEEE Press, January 2003 Chapter 6: Low-Energy System Issues

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic2 Switching Energy Clock is the highest activity signal  Switching energy is dominant  - probability of a 0-1 transition C i – total switched capacitance at node i V swing (i) – voltage swing at node i V DD – supply voltage N – number of nodes Energy is best reduced by scaling down V DD, but this also means performance degradation

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic3 Impact of Vdd on (a) delay, and (b) internal race immunity (0.25  m, light load). (Markovic et al. 2001), Copyright © 2001 IEEE (a)(b) (Delay is normalized to FO4 at its respective V DD. FO4 as defined in this example increases with V DD  performance degradation) Pulsed Designs Scale the Best with V DD

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic4 Other Energy Reduction Techniques Low-Swing Circuit Techniques Reduced-swing Clk drivers CSE redesign N-only CSEs with Low-Vcc Clk Clock Gating Global Local Dual-Edge Triggering Latch-mux Pulsed-latch Flip-flop

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic5 Other Energy Reduction Techniques Low-Swing Circuit Techniques Reduced-swing Clk drivers CSE redesign N-only CSEs with Low-Vcc Clk Clock Gating Global Local Dual-Edge Triggering Latch-mux Pulsed-latch Flip-flop

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic6 Clock driver for half-swing clocking (Kojima at al. 1995), Copyright © 1995 IEEE Low-Swing Clocking, Option #1: Clock Driver Re-design 50% power reduction with half-swing clock (minus some penalty in clock drivers)

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic7 Reduced clock-swing flip-flop (Kawaguchi and Sakurai, 1998), Copyright © 1998 IEEE Low-Swing Clocking, Option #2: CSE Re-design PMOS does not fully turn-off

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic8 N-Only clocked M-S latch Low-Swing Clocking, Option #3: N-only CSEs N-only clocked transistors, M-S Latch Example (N 1 and N 2 improve pull-up on S M )

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic9 Other Energy Reduction Techniques Low-Swing Circuit Techniques Reduced-swing Clk drivers CSE redesign N-only CSEs with Low-Vcc Clk Clock Gating Global Local Dual-Edge Triggering Latch-mux Pulsed-latch Flip-flop

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic10 (a) Nongated clock circuit, (b) gated clock circuit. (Kitahara et al. 1998), Copyright © 1998 IEEE Clock Gating, Option #1: Global Clock Gating Used to save clocking energy when data activity is low Time-mux (no gating!) Global Clk Gating

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic11 Data-transition look-ahead latch (Nogawa and Ohtomo, 1998), Copyright © 1998 IEEE Clock Gating, Option #2: Local Clock Gating

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic12 Conditional capture flip-flop (Kong et al. 2000), Copyright © 2000 IEEE Local Clock Gating, Another Example

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic13 Other Energy Reduction Techniques Low-Swing Circuit Techniques Reduced-swing Clk drivers CSE redesign N-only CSEs with Low-Vcc Clk Clock Gating Global Local Dual-Edge Triggering Latch-mux Pulsed-latch Flip-flop

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic14 Dual-edge-triggered latch-mux design Dual-Edge Triggering, Option #1: Latch-Mux Used to save clocking energy regardless of data activity!

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic15 Dual-edge-triggered latch-mux circuit (Llopis and Sachdev, 1996), Copyright © 1996 IEEE DET Latch-Mux: Circuit Example

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic16 Dual-edge-triggered pulsed-latch design Dual-Edge Triggering, Option #2: Pulsed-Latch

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic17 Pulsed-latch: (a) single-edge-triggered; (b) dual-edge-triggered DET Pulsed-Latch: Circuit Examples

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic18 Dual-edge-triggered flip-flop design Dual-Edge Triggered Flip-Flop

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic19 DET symmetric pulse-generator flip-flop DET Flip-Flop: Circuit Example

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic20 H-tree clock distribution network Clock Distribution

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic21 Clocking power in single- and dual-edge-triggered systems Clocking Power: SET vs. DET

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic22 Glitch Robust Design

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic23 Comparison of average glitching energy in CSEs (Markovic at al. 2001), Copyright © 2001 IEEE Average Glitching Energy in CSEs

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic24 Glitching energy as a percentage of switching energy in representative CSEs showing the greatest glitch sensitivity of the gated designs Comparison of E glitching and E switching

Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic25 Summary Energy best reduced by V DD scaling Penalty in performance Reducing Clk swing only reduces E Clk Still penalty in performance Clock gating Reduces E Clk at low-activity No penalty in perf. if gating is outside crit-path Dual-Edge Triggering Reduces E Clk ideally by 2x Small or no performance degradation