French 207 MAPLD 2005 Slide 1 Integrated Tool Suite for Post Synthesis FPGA Power Consumption Analysis Matthew French, Li Wang University of Southern California, Information Sciences Institute Tyler Anderson, Michael Wirthlin Brigham Young University

French 207 MAPLD 2005 Slide 2 Power Tools: Goals Push power analysis, visualization, and optimization to front of the tools chain: –Analyze power consumption at logic simulation with two levels of accuracy Pre-place-and-route, using heuristic estimates based on fanout Back-annotated with precise post-place- and-route RC data –Visualize by providing intuitive views to help the designer rapidly find and correct inefficient circuits, operating modes, data patterns, etc. –Optimize systems by automatically identifying problem paths and suggesting improvements Benefits –Closer to logical level and design entry –Power profiling during functional simulation –Early estimation before place and route –Automatic specific resource utilization power details –Facilitates high level design alternative exploration FPGA Tool Flow Proposed Power Tool Entry Point Current Power Tool Entry Point

French 207 MAPLD 2005 Slide 3 Tool Backbone: JHDL & EDIF Parser Leverage JHDL simulation Environment with EDIF Parser circuit manipulation JHDL –Java-based structural design tool for FPGAs –Circuits described by creating Java Classes –Design libraries provided for several FPGA families – JHDL design aides –Logic simulator & waveform viewer –Circuit schematic & hierarchy browser –Module Generators Circuit designer does not need to know Java! JHDL Data Structure EDIF Netlist EDIF Data Structure Manipulation Tools EDIF Parser 3 rd Party Tools EDIF Parser –Supports multiple EDIF files –Virtex2 libraries and memory initialization –Support for “black boxes” –No JHDL wrapper required – –Verified: Synplicity, Synplcity Pro, Coregen, System Generator, Chipscope JHDL Environment EDIF Parser

French 207 MAPLD 2005 Slide 4 Power Visualization Tool Two views: –Instantaneous vs. cumulative power consumption over time –Sorted tree view of “worst offenders” Integrated “cross-probing” with existing JHDL tools –Unified Environment –Allows Experimentation –Smart Re-use of CPU Memory Help rapidly identify inefficient circuits and operating modes Per-cell / per-bit granularity Simulation trigger on power specification Cross Probing

French 207 MAPLD 2005 Slide 5 Post Synthesis Level Power Modeling Power Modeling –Quiescent power based on total circuit size –Dynamic Power Toggle Rates (Data Dependant) Components Used Routing Interconnect –Actual quiescent and dynamic power not known until circuit is placed and routed Leverage existing JHDL tool environment –Toggling rates derived from simulator Will lose glitching information –Components known from EDIF or JHDL primitives Component capacitance imported from Xpower –How to model routing interconnect? Do not have exact routing information at synthesis Routing tools can pick different route each iteration –Interconnect length and combinations vary ComponentCap (pF) ComponentCap (pF) FF1.21LUT1.0 SRL3.0LD1.0 INV1.0AND1.0 RAM1.0MULT17.2 DLL40.0IBUF1.0 BUFG6.0BRAM59.0 Xpower Component Capacitance InterconnectCap (pF) Long Line11.8 Hex Line0.59 Double Line0.44 Direct Connect0.29 Xpower Interconnect Capacitance

French 207 MAPLD 2005 Slide 6 Capacitance vs Fanout Fanout model well correlated Secondary fit line corresponds to Macros High variance at low fanout Achieving 4.3% average error, 16% variance Explored device utilization models as well Placement Macros

French 207 MAPLD 2005 Slide 7 Resulting Power Tool Flow Source Code Synthesis Map Place & Route Xpower Bitgen EDIF Parser JHDL Power Analysis & Visualization Virtex II Power Model Routed Circuit Model EDIF VHDL Verilog JHDL Xilinx Tool Flow.ncd To Target.pwr Power Tools

French 207 MAPLD 2005 Slide 8 Power Optimization Approach Influence Xilinx Place&Route tools for power efficiency –Minimize clock/wire lengths of high power nets Use power analysis tools to identify hot-spots and generate constraints –Timing constraints on non-clock signals –Location constraints on sink flip-flops of clock signals Timing Constraints –Over-constrain timing for power –Achieving up to 12% power reduction Location Constraints –Pares clock tree –Achieving up to 23% power reduction –Several placement strategies Not violating original circuit timing specifications Timing Constraint (ns) Placement Constraint (X,Y) Unconstrained Constrained

French 207 MAPLD 2005 Slide 9 Conclusions Post-synthesis level power modeling is feasible –Some accuracy trade-offs inevitable –Quicker power results enable Capability to determine power specifications early in the design flow Feedback on design-level circuit power ramifications Tighter feedback loop to designer for more design iterations Optimization –Preliminary results encouraging –Tools do not alter original circuit functionality & use COTS inputs –Developing optimization algorithms & routines Tools are open source: This research made possible by a grant from the NASA Earth-Sun System Technology Office