Critical Power Slope: Understanding the Runtime Effects of Frequency Scaling Akihiko Miyoshi †,Charles Lefurgy ‡, Eric Van Hensbergen ‡, Ram Rajamony ‡, Raj Rajkumar † † Real-Time and Multimedia Systems Lab Dept. of Electrical and Computer Engineering Carnegie Mellon University ‡ Austin Research Laboratory IBM

The Question Operating Points –[600MHz,6V], [525MHz,4.2V],[450MHz,2.8V],[375MHz,2V],[300MHz, 1.7V], [225MHz,1.5V],[150MHz,1.45V] Where should I operate (for energy efficiency)? –Dynamic Voltage Scaling (DVS) algorithms –Lowest performance without sacrificing user/application requirement Why lowest performance is not always the best –Even for voltage scaling systems

Energy Efficiency... power time Watts Low frequencyHigh frequency

Majority of OS policies assume Not always the case! –When it is not the case? –How do we determine this? Assumption < Watts

Motivation – < : not always true –How do we choose which operating points to use? Measurement results Analytical model: Critical Power Slope Analysis on voltage scaling systems Conclusion Outline

Power Management Techniques Provides multiple operating points –[600MHz,6V],[450MHz,2.8V],[300MHz, 1.7V]…etc Three empirical data points –Frequency Scaling PowerPC 405GP –Clock Throttling Pentium with ACPI –Voltage Scaling Strong ARM SA-1100 Note: We are not making any statement on the benefits of these techniques! –These are merely samples which real systems use to manage power.

Basic Results Runtime and frequency –CPU intensive workload: inverse relationship Power and frequency –Frequency scaling, clock throttling processors CPU active: linear relationship CPU idle: constant m: slope CPU active CPU idle Power Frequency

Energy Consumption Compare energy consumption at different operating points –Same workload W –Same amount of time t power time

Energy consumption (Pentium L1 cache read hit) 2490J 2591J 174.3sec

Energy consumption (PPC L1 cache read hit) 136J 66.4sec 162J

Measurement Results Results consistent with different workloads –Register, L1 cache, memory, disk accesses –Web server (Pentium) Pentium –Highest frequency always energy efficient PowerPC –Lowest frequency always energy efficient Why? –What happens on voltage scaling systems?

Motivation –Which operating points should we consider? Measurement results –Pentium: highest performance better –PowerPC: lowest performance better Analytical model: Critical Power Slope Analysis on voltage scaling systems Conclusion Outline

CPU intensive workload W Frequency –Assume utilization of system = 1 – units of time to complete W –Energy consumed At frequency –Time to compute W: –Remaining extra idle time: Characterization

–Power increases linearly with frequency –m: slope Is energy efficient?? –True if –Depends on m Critical Power Slope

Use slope m to characterize system –Find hypothetical m for and call it Critical Power Slope (CPS) Critical Power Slope cont’d

What does it mean? Freq Power

If –Energy efficient to run at higher freq. –Pentium If –Energy efficient to run at lower freq. –PowerPC Implications of CPS <

J.Pouwelse, K.Langendoen, and H. Sips, “Dynamic Voltage Scaling on a Low-Power Microprocessor”, MOBICOM2001 Voltage Scaling Processors (Strong Arm SA-1100)

Look at every operating point at frequency If –Energy efficient at higher frequency than If –Energy efficient at lower frequency than CPS for voltage scaling system

Analysis on SA-1100 Above 74MHz At 74MHz Below 74MHz Energy Inefficient below 74MHz!

Summary Power Frequency Power Frequency Power Frequency PentiumPowerPC SA-1100 CPS: Characterizes the runtime trade-off of power management techniques

Conclusion Which operating points should we consider? –Traditional DVS algorithms attempt to go to lowest frequency –Not always the best choice Critical Power Slope Identifies energy inefficient operating points Can be used to inform OS (DVS algorithms) of operating points it should not consider