LCWS08, Chicago, November 2008 Ladislav Andricek, MPI fuer Physik, HLL 1 DEPFET Active Pixel Sensors - Status and Plans - Ladislav Andricek for the DEPFET.

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Presentation transcript:

LCWS08, Chicago, November 2008 Ladislav Andricek, MPI fuer Physik, HLL 1 DEPFET Active Pixel Sensors - Status and Plans - Ladislav Andricek for the DEPFET Collaboration (

LCWS08, Chicago, November 2008 Ladislav Andricek, MPI fuer Physik, HLL 2 DEPFETs for the ILC VXD Prototype System with DEPFETs (450µm), CURO and Switcher many test CERN and Desy: 450 µm  goal S/N ≈ 50 µm sample-clear-sample 320 ns  goal 50 ns s.p. res. with 24 µm pixels: µm  goal ≈ µm Thinning technology established, thickness can be adjusted to the needs of the experiment (~20 µm … ~100 µm), design goal 0.11 % X 0 radiation tolerance tested with single pixel structures up to 1 Mrad and ~10 12 n eq /cm 2 In Summary: Achievements and Status In this talk:  Some new features of the latest DEPFET production  Update on thinning/ladder R&D  Next Steps

LCWS08, Chicago, November 2008 Ladislav Andricek, MPI fuer Physik, HLL 3 The latest DEPFET Generation ‘PXD5’  Mostly use ‘baseline’ linear DEPFET geometry  Build larger matrices Long matrices (full ILC drain length) Wide matrices (full Load for Switcher Gate / Clear chips)  Try new DEPFET variants: -: reduce clear voltages -: Very small pixels (20µm x 20µm) -: Capacitively Coupled Common Clear Gate -: Increase internal amplification (g q ) 512x512 matrix

LCWS08, Chicago, November 2008 Ladislav Andricek, MPI fuer Physik, HLL 4 Capacitively Coupled Common Clear Gate Gate Clear Clear Gate Gate Clear Clear Gate Gate Clear Clear Gate std.: clocked clear gate ILC: common clear gate fast and safe clear: cap. coupled clear gate 109 Cd spectrum (22keV, 6000 e - ) taken with 128x64 matrix poly2 n+ implant

LCWS08, Chicago, November 2008 Ladislav Andricek, MPI fuer Physik, HLL 5 Internal amplification g q As long as noise is dominated by r/o chip  S/N linear with g q PXD4 has L=6μm, some matrices in PXD5 have now L=4μm  expect factor 2 better S/N effective gate length L eff (µm) g q (pA/e-) simulation at I D =50 µA L eff = L - 2 x under etching of 1.2µm (neglecting short channel effects) PXD4: measurement and simulation PXD5: single pixel measurement S.Rummel

LCWS08, Chicago, November 2008 Ladislav Andricek, MPI fuer Physik, HLL 6 A new r/o chip - DCD (Uni Heidelberg) DCD: Drain Current Digitizer -: improved input cascode (regulated) and current memory cells -: integrated 8bit current based ADC per channel, 12.5 MHz sampling rate but needs 600MHz Clock -: designed for 40 pF load at the input (5cm Drain line), 12 µm r/o pitch -: f/e noise: add 37nA for memory cells   at 40pF with g q =500pA/e  100 e- ENC in total -: layout for bump bonding, rad. hard design -: power consumption per channel 3.6 mW (measured) -: digital hit processing done with 2nd digital chip (DHP) Test chip DCD2: 6X12 channels

LCWS08, Chicago, November 2008 Ladislav Andricek, MPI fuer Physik, HLL 7 Thinning Technology Compatibility with the main production line tested So far for ILC: -: mechanical samples -: test structures (diodes) on SOI wafers Presented the first time about 6 years ago, this technique found now its way into other projects: -: production of thin (75 and 150 μm) ATLAS pixel sensors for sLHC -: first production of Geiger-mode APDs on 70 μm top layer Top Wafer Handle Wafer a) oxidation and back side implant of top wafer b) wafer bonding and grinding/polishing of top wafer c) process  passivation open backside passivation d) anisotropic deep etching opens "windows" in handle wafer

LCWS08, Chicago, November 2008 Ladislav Andricek, MPI fuer Physik, HLL 8 Large area diodes 4 "full size" 1 st layer ILC ladders 100x13 mm 2, 1 and 3 mm frame along the long side Diodes with various areas Alignment marks in BOX to find the partial p-implant after bonding IR photo: 80 nm step in BOX

LCWS08, Chicago, November 2008 Ladislav Andricek, MPI fuer Physik, HLL 9 Large area diodes - characteristics

LCWS08, Chicago, November 2008 Ladislav Andricek, MPI fuer Physik, HLL 10 Large area diodes - characteristics

LCWS08, Chicago, November 2008 Ladislav Andricek, MPI fuer Physik, HLL 11 Large area diodes - characteristics

LCWS08, Chicago, November 2008 Ladislav Andricek, MPI fuer Physik, HLL 12 Large area diodes - characteristics

LCWS08, Chicago, November 2008 Ladislav Andricek, MPI fuer Physik, HLL 13 Sensor + DCD + DHP  MultiChipModule (Ladder) DEPFET Ladder New DCD Hybrid (10 layers!!) DCD full speed r/o system +

LCWS08, Chicago, November 2008 Ladislav Andricek, MPI fuer Physik, HLL 14 Baseline: Gold Stud Bump Bonding

LCWS08, Chicago, November 2008 Ladislav Andricek, MPI fuer Physik, HLL 15 Baseline: Gold Stud Bump Bonding

LCWS08, Chicago, November 2008 Ladislav Andricek, MPI fuer Physik, HLL 16 The next steps.... See DEPFET Backup Document at Many years of R&D for the ILC VXD (see review fall 2007)  The DEPFET is ready to be used in precision vertex detectors

LCWS08, Chicago, November 2008 Ladislav Andricek, MPI fuer Physik, HLL 17 Super-B Factory at KEK (Masa Yamauchi, Spring 2008) and pixels! ~2012 ~202X

LCWS08, Chicago, November 2008 Ladislav Andricek, MPI fuer Physik, HLL 18 The Vertex Detector at SuperBelle (LoI Layout) -: 2 thin pixel layers at 1.3 cm and 1.6 cm (subject to optimization) -: 4 layers with double sided Si-strip detectors -: Angular coverage 17°<θ < 150°, slanted at the end ~10cm

LCWS08, Chicago, November 2008 Ladislav Andricek, MPI fuer Physik, HLL 19 From ILC to superKEKB  Pixel Size Super KEKB is more challenging than ILC ILC super KEKB Occupancy hits/µm 2 /sec 0.4 hits/µm 2 /sec (initial) Radiation 1 Mrad/year Duty Factor 1/200 ~1 ILC needs excellent IP resolution over a large momentum range: -: Low material  thin ladders down to the very forward region -: Good single point resolution (  = 3..5 µm)  small pixels (24µm) superKEKB is dominated by low momentum tracks (< 1GeV/c): -: Low material!!! -: but IP resolution always dominated by MS error (beampipe & 0.14%X 0 Si  ~ 9 µm at 1 GeV/c  Modest intrinsic resolution of  ~ 10 µm sufficient: pixels could be larger

LCWS08, Chicago, November 2008 Ladislav Andricek, MPI fuer Physik, HLL 20 ILC VXD  SuperBelle PXD Some important numbers for the baseline layout: four-fold read out : frame rate 100 kHz, 80ns/row sensitive region : 1.15x7.25 cm 2 (L1), 1.15x9.26 cm 2 (L2) material budget : 0.15% X 0 (incl. frame, chips, bumps) power/module : DEPFETs ~ 0.5 W Switcher ~ 0.2 W DCD ~ 3 W on each ladder end

LCWS08, Chicago, November 2008 Ladislav Andricek, MPI fuer Physik, HLL 21 ….towards sBelle ladders DEPFET incl. rad. tolerance Thinning Mechanics chips/system development thin Me./El. Samples interconnections on & off module Engineering ladder support ASIC production: UMC, AMS, IBM, TSMC…. use the best available process DEPFET prototyping and series production of the sensors at the MPI Halbleiterlabor tech. tests PXD6 SWITCHER3 sBelle PXD SWITCHER4 DCD2 DCD4? SWITCHER5? DCD3 PXD7

LCWS08, Chicago, November 2008 Ladislav Andricek, MPI fuer Physik, HLL 22 Summary -: Tests of the latest DEPFET production are in full swing. We are looking forward to see the new features like capacitive coupling of the clear gate and shorter gate lengths in next year's test beam! -: The DEPFET is ready to be used as a high precision vertex detector at SuperBelle. This Project will certainly boost the R&D for ILC DEPFETs. The next production (PXD6) will start January 2009  the first thin DEPFETs for SuperBelle and ILC!