Detecting Errors Using Multi-Cycle Invariance Information Nuno Alves, Jennifer Dworak, and R. Iris Bahar Division of Engineering Brown University Providence, RI Kundan Nepal Electrical Engineering Dept. Bucknell University Lewisburg, PA Design, Automation, and Test in Europe, April 20-24, 2009

Motivation Errors in ICs are increasing –Particle strikes, temperature, power, noise, process variations, test escapes, etc. Previously, we have proposed using logic implications for online error detection during a single clock cycle What happens if we consider implications across time cycles?

Outline Introduction & Background Logic Implications for Error Detection Multi-Cycle Implications Experimental Results Conclusions

Outline Introduction & Background Logic Implications for Error Detection Multi-Cycle Implications Experimental Results Conclusions

Other Work Triple Modular Redundancy Logic Duplication Re-Execution in Multiple Threads Codes (Parity, Berger, Bose Lin, etc.) High Level Fault Assertions Fault Masking Checking the Outputs Against a Subset of the Truth Table

Our Approach Find natural expected relationships and check for their violation. Water should be blue…. Not brown… In circuits, expected relationships at the gate level consist of logic implications.

Outline Introduction & Background Logic Implications for Error Detection Multi-Cycle Implications Experimental Results Conclusions

Implications Naturally Occur in Circuits n1 n2 n3 n4 n5 n6 n7 n n5 = 1 → n8 = 0

Implication Violations Can Be Used to Detect Errors ERROR n1 n2 n3 n4 n5 n6 n7 n8 n5=1 n8=0 Appropriate checker logic can detect multiple errors with a single implication.

Implication Violations Can Be Used to Detect Errors ERROR n1 n2 n3 n4 n5 n6 n7 n8 n5=1 n8=0 Appropriate checker logic can detect multiple errors with a single implication. sa1

So….what’s the problem?

We have too many implications! How do we efficiently find them and which ones should we use?

Implication Algorithm Gate-level implications can be found automatically …without functional knowledge of the circuit.

What determines which faults an implication may cover?

Potential Spatial Fault Coverage Each implication can only cover a limited area of the circuit…. P Q Direct Path P=0 → Q=0 Faults along the path may be detected P Q P Q P=1 → Q=1 Faults along reconverging paths may be detected Reconvergent Fanout P Q Divergent Fanout P Q Q=0 → P=0 Faults along paths to common ancestors may be detected

Implications cannot cover any sites downstream of both implication points!

Limitations of Single-Cycle Implications Implications may not exist to cover faults far downstream—e.g. close to: –Flip-flops –Primary Outputs It is possible for no useful implications to exist in a single cycle Optimal timing of capture is difficult Many of these issues are alleviated if we consider multi-cycle implications

Outline Introduction & Background Logic Implications for Error Detection Multi-Cycle Implications Experimental Results Conclusions

Multi-Cycle Implications Sequential Circuit Containing No Non-Trivial Implications in Combinational Logic Time Frame Expansion Logic Value in First Clock Cycle Implies a Value at a Different Site in the Second Clock Cycle B 1 = 0 → F 2 = 0

Multi-Cycle Checker Hardware B 1 = 0 → F 2 = 0 Checker hardware requires state to be held between first and second cycle….

Spatial Coverage of Multi-Cycle Implications Good spatial coverage can be achieved near flip-flops Logical distance may increase between implication sites Delays captured at flip-flops in cycle t can be detected without complex timing P Q Cycle tCycle t + 1 Advantages:

Outline Introduction & Background Logic Implications for Error Detection Multi-Cycle Implications Experimental Results Conclusions

Experimental Setup ISCAS ’89 benchmark circuits Zchaff SAT solver to validate implications Three sets of implications per circuit –First cycle Both implication sites in cycle 1 Obtained with single cycle analysis & unrestricted inputs –Second cycle Both implication sites in cycle 2 Obtained with time frame expansion –Cross cycle One site per cycle Obtained with time frame expansion

So, how many implications exist?

What is the distance between implication sites?

How do the different implication classes compare for error detection (if we use all possible implications)?

Developing a Compressed Implication Set

What if we further tradeoff error coverage for reduced area overhead?

Outline Introduction & Background Logic Implications for Error Detection Multi-Cycle Implications Experimental Results Conclusions

Conclusions Implications can be used to effectively detect many errors at runtime –Without requiring functional knowledge of the circuit –Allowing tradeoffs to be made between error coverage and overhead Cross-cycle implications cover faults that cannot be covered by single cycle implications Even though they have larger overhead, cross cycle implications are often an “optimal” choice When optimizing for low area overhead, more than 85% of the implications may be cross cycle

For Inquiring Minds

Implication Algorithm Gate-level implications can be found automatically …without functional knowledge of the circuit. Run Good Circuit Simulation with Random Vectors and Monitor Site Values… A,B A,C A,D A=0 → C = 0

Implication Algorithm Gate-level implications can be found automatically …without functional knowledge of the circuit. Using a SAT solver (such as Zchaff)

Implication Algorithm Gate-level implications can be found automatically …without functional knowledge of the circuit. n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n10 = 0 → n13 = 0 n4 = 1 → n8 = 0

Implication Algorithm Gate-level implications can be found automatically …without functional knowledge of the circuit. Of all the patterns that will allow a fault to produce an error at an output, how many will each implication detect?

Implication Algorithm Gate-level implications can be found automatically …without functional knowledge of the circuit.