A flexible simulator for control- dominated distributed real-time systems Johannes Petersson IDA/SaS/ESLAB Johannes Petersson IDA/SaS/ESLAB Master’s Thesis presentation Examiner Petru Eles Examiner Petru Eles Supervisor Paul Pop Supervisor Paul Pop

2 2 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation Outline  Introduction  Control-dominated systems  Modelling  Embedded system design  Simulation  A simulator for control-dominated systems  Experimental results  Conclusion and future work  Introduction  Control-dominated systems  Modelling  Embedded system design  Simulation  A simulator for control-dominated systems  Experimental results  Conclusion and future work

3 3 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation Introduction  Embedded systems  Motivation  Test for correctness  Validate timing behaviour  Cost, size and power reduction  Embedded systems  Motivation  Test for correctness  Validate timing behaviour  Cost, size and power reduction

4 4 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation Control-dominated systems Embedded systems Real-time systems Homogeneous or heterogeneous Real-time systems Homogeneous or heterogeneous Distributed R-T Systems Control-dominated systems

5 5 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation Control-dominated systems  System overview  Control function Desired output Actual output Leads to the need of iterative design steps

6 6 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation Modelling  System model  Distributed  Heterogeneous  Mapped  WCET  Scheduled  Distributed  Heterogeneous  Mapped  WCET  Scheduled

7 7 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation Modelling  Application model  Conditional Process Graph Processes Conditions Mapping Resources Sensors Actuators Functionality  Conditional Process Graph Processes Conditions Mapping Resources Sensors Actuators Functionality

8 8 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation P4P4 P4P4 P5P5 P5P5 P7P7 P7P7 P 13 P 15 First processor Second processor ASIC C C DD P0P0 P 18 P1P1 P1P1 P2P2 P2P2 P3P3 P3P3 P6P6 P6P6 P8P8 P8P8 P9P9 P9P9 P 10 P 11 P 12 P 14 P 16 P 17 C K K P0P0 P 18 P1P1 P2P2 P3P3 P6P6 P8P8 P9P9 P 10 P 11 P 12 P 14 P 16 P 17 Subgraph corresponding to DCK Conditional Process Graph

9 9 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation Embedded system design  Design flow  Design transformations  Functional partitioning  Allocation and mapping  Scheduling  Design flow  Design transformations  Functional partitioning  Allocation and mapping  Scheduling

10 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation Design flow  Design steps Simulation

11 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation Design transformations  Functional partitioning  Split processes  Merge processes

12 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation Design transformations  Allocation and mapping  Allocating resources  Mapping processes  Allocating resources  Mapping processes

13 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation Design tasks  Scheduling  Decide on a scheduling algorithm and perform the scheduling  Pre-emptive / non pre-emptive  Dynamic / static  Decide on a scheduling algorithm and perform the scheduling  Pre-emptive / non pre-emptive  Dynamic / static

14 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation Simulation introduction  Discrete- and continuous-time  Evaluate-update  Discrete events  Evaluate phase  Update phase  Evaluate-update  Discrete events  Evaluate phase  Update phase ActuatorP1P1 P2P2 Senso r P1P1 P2P2 ActuatorSensor

15 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation Related work  Simulators reviewed  True Time  The Network Simulator  SystemC’s simulator engine  Etc.  Extended Task Graphs (eTG)  Process graph with conditional constructs  eTG to SystemC translator Stephan Klaus, Automatic generation of scheduled SystemC models Doesn’t consider the conditional constructs Inspirational source  Simulators reviewed  True Time  The Network Simulator  SystemC’s simulator engine  Etc.  Extended Task Graphs (eTG)  Process graph with conditional constructs  eTG to SystemC translator Stephan Klaus, Automatic generation of scheduled SystemC models Doesn’t consider the conditional constructs Inspirational source

16 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation SystemC  Basics  Provides an evaluate-update simulation engine  Possible to implement any scheduling policy  Models both hardware and software  Work at different abstraction levels  Provides an evaluate-update simulation engine  Possible to implement any scheduling policy  Models both hardware and software  Work at different abstraction levels  A C/C++ library  A de facto open source standard  A modelling platform and language for system-level co-design  Spans from concept to implementation  A de facto open source standard  A modelling platform and language for system-level co-design  Spans from concept to implementation

17 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation Module 1Module 2 SystemC Concepts  Hierarchical modules  May contain processes and other modules SC_MODULE  May contain processes and other modules SC_MODULE  Communication  The modules and processes communicate through signals passed through ports  Three types of processes  Asynchronous-function (SC_METHOD)  Asynchronous-thread (SC_THREAD)  Synchronous-thread (SC_CTHREAD)  Asynchronous-function (SC_METHOD)  Asynchronous-thread (SC_THREAD)  Synchronous-thread (SC_CTHREAD)

18 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation A simulator for control-dominated systems  Overview

19 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation A simulator for control-dominated systems  Representation Tasks.xml Task_01 5 Cond_A Sensor_01 null Tasks.xml Task_01 5 Cond_A Sensor_01 null Graph.xml Task_01 5 Arc_01 1 Task_01 Task_02 Graph.xml Task_01 5 Arc_01 1 Task_01 Task_02 Allocation.xml PR2 Task_01 B1 Arc_01 Allocation.xml PR2 Task_01 B1 Arc_01

20 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation A simulator for control-dominated systems  Scheduling Schedule.xml 10 !Cond_A Cond_B Task_03 Schedule.xml 10 !Cond_A Cond_B Task_03 processTrueCC & DC & -D P10 P25 P414 P545 P65150 P73

21 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation A simulator for control-dominated systems  cpg2sc  Tasks  Stored in one SC_Module Consist of several SC_Thread  Controller  Stored in one SC_Module Consist of one SC_Thread  Main program  One SC_Main function Binds all ports to signals Starts the simulation  Tasks  Stored in one SC_Module Consist of several SC_Thread  Controller  Stored in one SC_Module Consist of one SC_Thread  Main program  One SC_Main function Binds all ports to signals Starts the simulation

22 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation Implementation A day at work.

23 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation Simulation results  Basic setup: Part of a Cruise Controller

24 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation Simulation results  Functional partitioning Throttle angle Fuel injection

25 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation Simulation results  Conditions and resource allocation Fuel injection

26 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation Simulation results  Mapping Fuel injection

27 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation Simulation results  Waveform diagram

28 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation Conclusion and future work  Conclusion  Implemented a simulator for control dominated distributed real-time systems  SystemC used as the simulator’s engine  Successfully used in evaluating several design transformations  Future work  Add more scheduling policies Fixed-priority pre-emptive scheduling  Refine communication TTP, CAN, etc.  Conclusion  Implemented a simulator for control dominated distributed real-time systems  SystemC used as the simulator’s engine  Successfully used in evaluating several design transformations  Future work  Add more scheduling policies Fixed-priority pre-emptive scheduling  Refine communication TTP, CAN, etc.

29 Johannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation Thank you  Thanks to everybody for listening  Thanks to Petru Eles and Paul Pop  Thanks to everybody for listening  Thanks to Petru Eles and Paul Pop