Final Design Review of a 1 GHz LNA / Down-Converter Charles Baylis University of South Florida April 22, 2005

LNA Design Summary IBM SiGe Design Kit - 4 layers of metal Load resistance = 50 ohms (Filter) Feedback Resistor from collector to base stabilizes circuit, provides better matching For feedback configuration I C = 6 mA, R F = 460 ohms (initial – values were changed for final schematic.

LNA Design Summary Power Consumption: Current through gain transistor + 1 mA reference current through current mirror. LC Match on Input/Output “De-Q” Inductors with resistors to improve bandwidth.

LNA Schematic 9.3 pF 6.5 nH 83 pF 560 Ω 27 pF 1.4 kΩ 7.3 nH 4.5 pF 650 Ω Input Output Ground Vcc

LNA Gain

LNA Noise Figure

LNA Input IP3

LNA Input/Output Match

LNA Compliance Reqt.Spec. MinSpec. MaxMinimumMaximumPass/Fail DC Current-10 mA-9.8 mAPass Gain14.5 dB17.5 dB16.5 dB16.9 dBPass Noise Figure -2.5 dB2.3 dB2.8 dBFail Input IP3-20 dBm--2.7 dBm-Pass Uncond. Stability ----Pass Input Return Loss 15.0 dB-15.7 dB20.9 dBPass Output Return Loss 15.0 dB dBPass

LNA Compliance-Temperature Reqt.Spec. Min Spec. Max MinimumMaximumPass/Fai l DC Current-10 mA9.3 mA (-20˚)10.2 mA (70˚)Fail Gain14.5 dB17.5 dB16.0 dB (70˚)17.5 dB (-20˚)Pass Noise Figure -2.5 dB1.93 dB (-20˚)3.24 dB (70˚)Fail Uncond. Stability ----Pass Input Return Loss 15.0 dB-14.7 dB (-20˚)21.6 dB (70˚)Fail Output Return Loss 15.0 dB-14.0 dB (70˚)31.4 dB (-20˚)Fail

LNA Compliance - Bias Reqt.Spec.MinSpecMaxMinimumMaximumPass/Fail DC Current-10 mA8.1 mA (2.7 V)11.6 mA (3.3 V) Fail Gain14.5 dB17.5 dB14.9 dB (2.7 V) 18.0 dB (3.3V) Fail Noise Figure -2.5 dB2.3 dB (3.3 V)2.9 dB (2.7 V) Fail Uncond. Stability ----Pass Input ReturnLoss 15.0 dB-12.9 dB (3.3 V) 22.2 dB (3.3V) Fail Output ReturnLoss 15.0 dB-10.7 dB (2.7 V) 30.3 dB (3 V) Fail

LNA Layout LNA In Vcc LNA Out

Mixer Design Approach f RF = 1 GHz, f LO = 860 MHz, f IF = 140 MHz Conversion gain = 9 dB = 2.82 Output Resistance = 50 Ω  R L = 25 Ω Solve conversion gain equation for g m (gives starting value for current I C1 ).. Use LC network for input matching.

Mixer Design Approach Noise figure improved by shrinking reference transistor for current mirror (and associated current). Also, beta helper transistor size was increased. As in LNA, “de-Q” inductors with shunt resistors to improve bandwidth.

Mixer Schematic Input Out +Out kΩ 7 kΩ Vcc Ground 7.8 nH 3.7 pF 250 Ω 83 pF LO+LO-

Mixer Conversion Gain

Mixer Input IP3

Mixer Input/Output Match Input Reflection CoefficientOutput Reflection Coefficient

Mixer Noise Figure

Mixer Compliance Specified Gain and Bandwidth Reqt.Spec. MinSpec. MaxMinimumMaximumPass/Fail DC Current-25 mA-12.4 mAPass Gain7.5 dB10.5 dB9.3 dB10.0 dBPass Noise Figure -11 dB9.0 dB10.7 dBPass Input IP3-15 dBm Pass Input Return Loss 15.0 dB-15.2 dB26.4Pass Output Return Loss 15.0 dB-31.5 dB31.2 dBPass

Mixer Compliance - Temperature Specified Gain and Bandwidth Reqt.Spec. MinSpec. MaxMinimumMaximumPass/Fail DC Current-25 mA11.47 mA13.3 mAPass Gain7.5 dB10.5 dB7.9 dB11.1 dBFail Noise Figure -11 dB7.1 dB11.59 dBFail Input Return Loss 15.0 dB- 31.7Fail Output Return Loss 15.0 dB-31.2 dB31.6 dBPass

Mixer Compliance - Bias Specified Gain and Bandwidth Reqt.Spec. MinSpec. MaxMinimumMaximumPass/Fail DC Current-25 mA9.9 mA15.1 mAPass Gain7.5 dB10.5 dB8.2 dB10.7 dBFail Noise Figure -11 dB7.9 dB10.9 dBPass Input Return Loss 15.0 dB-13.7 dB45.4Fail Output Return Loss 15.0 dB-27.8 dB40.2 dBPass

Mixer Layout Vcc Out - Out + LO - LO +- Mixer In

LNA DRC and LVS

Mixer DRC and LVS

Conclusion Only LNA noise figure does not meet specification at nominal temperature and bias. Design has been run through multiple simulations to test its robustness.