CHAP3: MOS Field-Effect Transistors (MOSFETs) 1

FETs vs. BJTs Similarities: • Amplifiers • Switching devices • Impedance matching circuits Differences: • FETs are voltage controlled devices. BJTs are current controlled devices. • FETs have a higher input impedance. BJTs have higher gains. • FETs are less sensitive to temperature variations and are more easily integrated on ICs. • FETs are generally more static sensitive than BJTs. FET Types •JFET: Junction FET •MOSFET: Metal–Oxide–Semiconductor FET D-MOSFET: Depletion MOSFET E-MOSFET: Enhancement MOSFET

FET Operating Characteristics JFET operation can be compared to a water spigot. The source of water pressure is the accumulation of electrons at the negative pole of the drain-source voltage. The drain of water is the electron deficiency (or holes) at the positive pole of the applied voltage. The control of flow of water is the gate voltage that controls the width of the n-channel and, therefore, the flow of charges from source to drain. FET Operation: The Basic Idea There are three basic operating conditions for a JFET: • VGS = 0, VDS increasing to some positive value • VGS < 0, VDS at some positive value • Voltage-controlled resistor

FET ( Field Effect Transistor) Few important advantages of FET over conventional Transistors Unipolar device i. e. operation depends on only one type of charge carriers (h or e) Voltage controlled Device (gate voltage controls drain current) Very high input impedance (109-1012 ) Source and drain are interchangeable in most Low-frequency applications Low Voltage Low Current Operation is possible (Low-power consumption) Less Noisy as Compared to BJT No minority carrier storage (Turn off is faster) Self limiting device Very small in size, occupies very small space in ICs Low voltage low current operation is possible in MOSFETS Zero temperature drift of out put is possible

Types of Field Effect Transistors (The Classification) JFET MOSFET (IGFET) n-Channel JFET p-Channel JFET FET Enhancement MOSFET Depletion MOSFET n-Channel EMOSFET n-Channel DMOSFET p-Channel DMOSFET p-Channel EMOSFET

Fundamentals of FET sedr42021_0401a.jpg Figure Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3 mm, W = 0.2 to 100 mm, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.

Figure The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate.

sedr42021_0403.jpg Figure An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is determined by vGS. Specifically, the channel conductance is proportional to vGS – Vt’ and thus iD is proportional to (vGS – Vt) vDS. Note that the depletion region is not shown (for simplicity).

sedr42021_0404.jpg Figure The iD–vDS characteristics of the MOSFET in Fig. 4.3 when the voltage applied between drain and source, vDS, is kept small. The device operates as a linear resistor whose value is controlled by vGS.

sedr42021_0405.jpg Figure Operation of the enhancement NMOS transistor as vDS is increased. The induced channel acquires a tapered shape, and its resistance increases as vDS is increased. Here, vGS is kept constant at a value > Vt.

sedr42021_0406.jpg Figure The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS > Vt.

sedr42021_0407.jpg Figure: Increasing vDS causes the channel to acquire a tapered shape. Eventually, as vDS reaches vGS – Vt’ the channel is pinched off at the drain end. Increasing vDS above vGS – Vt has little effect (theoretically, no effect) on the channel’s shape.

Output or Drain (VD-ID) Characteristics of n-MOSFET Figure: Circuit for drain characteristics of the n-channel JFET and its Drain characteristics. Non-saturation (Ohmic) Region: The drain current is given by Saturation (or Pinchoff) Region: Where, IDSS is the short circuit drain current, VP is the pinch off voltage

Application1:

Application2: sedr42021_0420.jpg

Application3: Figure: (a) Circuit for Example. (b) The circuit with some of the analysis details shown. sedr42021_0423a.jpg

Output or Drain (VD-ID) Characteristics of n-JFET Figure: Circuit for drain characteristics of the n-channel JFET and its Drain characteristics. Non-saturation (Ohmic) Region: The drain current is given by Saturation (or Pinchoff) Region: Where, IDSS is the short circuit drain current, VP is the pinch off voltage

VD-ID Characteristics of EMOS FET Locus of pts where Saturation or Pinch off Reg. Figure: Typical drain characteristics of an n-channel JFET.

Figure: Transfer (or Mutual) Characteristics of n-Channel JFET Transfer (Mutual) Characteristics of n-Channel JFET IDSS VGS (off)=VP Figure: Transfer (or Mutual) Characteristics of n-Channel JFET

JFET Transfer Curve This graph shows the value of ID for a given value of VGS

Figure: Transfer (or Mutual) Characteristics of n-Channel FET Transfer (Mutual) Characteristics of n-Channel FET IDSS VGS (off)=VP Figure: Transfer (or Mutual) Characteristics of n-Channel FET

Biasing Circuits used for JFET Just as we learned that the BJT must be biased for proper operation, the JFET also must be biased for operation point (ID, VGS, VDS) In most cases the ideal Q-point will be at the middle of the transfer characteristic curve, which is about half of the IDSS. 3 types of DC JFET biasing configurations Fixed bias circuit Self bias circuit Potential Divider bias circuit

Fixed-bias Use two voltage sources: VGG, VDD + Use two voltage sources: VGG, VDD VGG is reverse-biased at the Gate – Source (G-S) terminal, thus no current flows through RG (IG = 0). + Vout _ + Vin _ Fixed-bias

Fixed-bias.. Loop 1 All capacitors replaced with open-circuit DC analysis All capacitors replaced with open-circuit Loop 1

Fixed-bias… 1. Input Loop By using KVL at loop 1: VGG + VGS = 0 VGS = - VGG Replace VGS = -VGG in Shockley’s Eq. ,therefore: 2. Output loop - VDD + IDRD + VDS = 0 VDS = VDD – IDRD 3. Then, plot graph by using Shockley’s Eq

Example : Fixed-bias Determine the following network: VGSQ IDQ VD VG VS

Solutions

Graphical solution for the network

Self-bias Using only one voltage source

DC analysis of the self-bias configuration. VGS + VRS = 0 Q point for VGS

Defining a point on the self-bias line. Vgs ID IDSS 0.3Vp IDSS/2 0.5Vp IDSS/4 Vp 0 mA

Sketching the self-bias line.

Example : Self-bias configuration

Solutions:

Sketching the device characteristics Vgs ID IDSS 0.3Vp IDSS/2 0.5Vp IDSS/4 Vp 0 mA

Sketching the self-bias line

Graphical Solutions: Determining the Q-point IDQ=2.6mA VGSQ=-2.6mV Q-point

Mathematical Solutions

Solutions IDQ = 2.6mA

Voltage-divider bias IG=0A A

Redrawn network

Sketching the network equation for the voltage-divider configuration.

Effect of RS on the resulting Q-point.

Example : Voltage-divider bias

Solutions

Determining the Q-point for the network IDQ=2.4mA VGSQ=-1.8mV

solutions How to get IDS, VGS and VDS for voltage-divider bias configuration by using mathematical solutions?

Exercise 3:

Drawing the self bias line

Determining the Q-point IDQ=6.9mA VGSQ=-0.35V

Exercise 4

Determining VGSQ for the network.

FET (n-channel) Biasing Circuits For Fixed Bias Circuit Applying KVL to gate circuit we get and Where, Vp=VGS-off & IDSS is Short ckt. IDS For Self Bias Circuit

FET Biasing Circuits Count… or Fixed Bias Ckt.

FET Self (or Source) Bias Circuit This quadratic equation can be solved for VGS & IDS

The Potential (Voltage) Divider Bias

A Simple CS Amplifier and Variation in IDS with Vgs

FET frequency Analysis: A common source (CS) amplifier is shown to the right. The mid-frequency circuit is drawn as follows: the coupling capacitors (Ci and Co) and the bypass capacitor (CSS) are short circuits short the DC supply voltage (superposition) replace the FET with the hybrid-p model The resulting mid-frequency circuit is shown below.

Figure: Simple NMOS amplifier circuit and Characteristics with load line.

Figure: Drain characteristics and load line

For drawing an a c equivalent circuit of Amp. Assume all Capacitors C1, C2, Cs as short circuit elements for ac signal Short circuit the d c supply Replace the FET by its small signal model

Analysis of CS Amplifier A C Equivalent Circuit Simplified A C Equivalent Circuit

Analysis of CS Amplifier with Potential Divider Bias This is a CS amplifier configuration therefore the input is on the gate and the output is on the drain.

Application 1

The small signal equivalent circuit of CS Amp.

Application 2 sedr42021_p04075.jpg

Application 3 sedr42021_p04077.jpg

Application 4 sedr42021_p04087.jpg

Application 5 sedr42021_p04088a.jpg

Application 6 sedr42021_p04099.jpg

Application 7 sedr42021_p04101.jpg Application: VIII

Application 8 sedr42021_p04104.jpg

Application 9 sedr42021_p04121a.jpg

FET Amplifier Configurations and Relationships: v + _ G V DD 1 SS 2 Common Drain (CD) Amplifier (also called “source follower”) L o D S Note: The biasing circuit is the same for each amp.