1 Basic Microcontroller System Chapter 2 Introduction to M68HC11 Hardware

2 Notation We will use special characters to represent a value in various number systems: For Hex numbers, we’ll use a $ –Ex: 3F 16 will be written as $3F For Binary numbers, we’ll use a % –Ex: will be written as %1010 For decimal numbers, we will a blank –Ex: = 23

3 Our Specific HC11 Our lab boards are populated with ICs (in U1) having the part number (visible on the package): –MC68HC11E9BCFN2 What this means (see Freescale HC11 Ref. Man., Figure 1-3): –MC- Motorola Corp., fully specified & qualified part –68- Numeric designator A broad spectrum of different Motorola CPUs all include this code –HC- High-density CMOS – Technology used in chip CMOS = Complementary Metal-Oxide-Semiconductor Operating voltage range V DD = 5V DC ± 10% –11- Numeric designator for a particular 8-bit MCU core & ISA –E- E-series line of microcontroller ICs, Includes 4 on-chip peripheral interface ports –9- IC version with a specific on-chip memory configuration Includes 512B RAM, 512B EEPROM, and 12K ROM on-chip –B- Buffalo monitor software included in ROM –C- Operating temperature range −40°C to 85°C. –FN- Package type: 52-pin Plastic Leaded Chip Carrier (PLCC) –2- Maximum clock speed (2 MHz)

4 Microcontroller-Based System Microcontroller e.g. M68HC11 To I/O CPU: Central Processor Unit I/O: Input/Output Memory: Program and Data Bus: Address signals, Control signals, and Data signals

5 Inside the CPU Block diagram of a simple, generic CPU: Instruction Decoder & CPU Controller Bus to memory system & I/O ports PC A B Registers Arithmetic- Logic Unit Write ports Read ports tristate buf mux Control signals Data path … CPU ALU Interrupt signals Control FSM mux

6 Typical CPU Operation Cycle 1.Fetch next sequential instruction (if not jumping): –Current PC t (program counter) sent to ALU, added to 1 –PC t +1 result is written to memory address bus, & to next PC t+1 –Memory system returns the instruction byte located at [PC t+1 ] –The controller unit reads and decodes the instruction Sets control signals appropriately to begin instruction execution 2.Instruction execution: –Data are moved around appropriately for the instruction Between memory, registers, and ALU (where data are processed) –The instruction’s execution may take 1 or more clock cycles Depending on the precise instruction type (and maybe on data). –Execution sequence performed by an FSM inside controller Or, by a microcode program… –A sequence of control words in a ROM inside the controller

7 Registers and Memory Arrays Introduction to Registers

8 D-FF Positive Edge Triggered DClk dd100 dd011 d011 d Symbol Equation (rising clock) Truth Table D-FF Stores 1 bit of data

9 4-bit Memory Register Stores 4 bits of data

10 8-bit Memory Register Stores 8 bits of data D[7..0] Q[7..0]

11 68HC11 Register Set Clock is implied

12 A,B and D Registers D Register is the 16 bit concatenation of the A and B registers. Ex: Let A=$23 and B=$EF then D=$23EF

13 Index Registers 16 bit registers

14 Stack Pointer The stack pointer is used to access a special section of memory called the Stack.

15 Condition Code Register Special Register used for control and provide arithmetic information to programmer and CPU. Condition Code Register

16 Program Counter The program counter points to the next byte which will be “fetched” from memory. It is not under direct control of the programmer.

17 Memory Used for Program and Data Storage

18 Memory Arrays Two major types –Volatile Data are lost when power is removed E.g. –SRAM – Static Random Access Memory –DRAM – Dynamic Random Access Memory Generically referred to as RAM (Random Access Memory) –Although non-volatile RAM exists as well –Non-Volatile Data are retained when power is removed E.g. –EEPROM – Electrically Erasable Programmable Read Only Memory –EPROM - Erasable Read Only Memory Generically referred to as ROM (Read Only Memory)

19 Memory Arrays RAM –Read from and write to RAM –Used for Data and Program Storage ROM –Only read from ROM –Used for Program Storage only Also store “Constant” data. –Special program stored in ROM “Boot” Program or “Loader” Program –This is the program that is executed when the microcontroller is “reset”

20 Memory Arrays To “access” memory we must have an “address” In the 68HC11, we have a 16 bit address bus, so –We can access 64K (64, ) or $10000 memory locations. –Addresses are numbered from $0000 to $FFFF Each memory location is 8 bits wide. Note: in general, –# of address bits = log 2 (# of memory locations) –Ex: Original IBM PC had a 1MByte address space # of address bits = log 2 (1024×1024) = log 2 (1,048,576) = 20 bits

21 68HC11 Memory Address Space

22 System ROM System RAM $0000 $FFFF User Program User Data Sample Memory Map User Stack Stack Data RAM

23 Default Memory Maps of HC11E9 (From the HC11E series datasheet)

24 Memory map on CME11E9-EVBU board, in the usual (expanded) mode (From the board’s manual)

25 Addressing Modes Microcontrollers/Microprocessors use a variety of “addressing modes” to refer to data which may be stored in a variety places, –Frequently at locations in the memory array. We’ll examine the addressing modes that are available in the 68HC11 –These are fairly representative of the sorts of modes that you will find in typical modern processors.

26 Addressing Modes Register (Inherent) Addressing Immediate Addressing Direct Memory Addressing –Extended Direct Memory Addressing Register Index Addressing Register Indirect Addressing Relative Addressing

27 Register (Inherent) Addressing The internal register set of the controller (or processor) is accessed. –Faster than regular memory access. –Use fewer bits to code this type of instruction Generally only a 1-byte opcode is needed. –Example: TAB = Transfer contents of register A to register B –Function (RTL semantics): B  A (B gets A) –Roughly equivalent C code: »register char a,b; … b = a; »if C variables “b” & “a” were allocated to registers b & a Machine code for TAB: only 1 byte, namely hex $16 = binary % Opcode for TAB.

28 Immediate Addressing The data for the instruction is coded right along with the instruction. That is, it immediately follows the instruction in memory. –It’s constant data. → It can be stored in ROM –Immediate data can generally be either 8-bit or 16-bit Although some instructions may only take 1 or the other –Use the # symbol to indicate immediate mode! Otherwise, you will be using Direct addressing –This is something completely different! –Examples of immediate addressing: LDAA #$64 - Load accumulator A with $64 (hex) –Machine code: 2 byte seq.: $86 (opcode), $64 (operand) –C code equivalent: register char a = 0x64; LDX #$ Load Register X with $1234 (Hex) –Machine code: 3 bytes: $CE, $12, $34. »opcode, MS (high) byte of $1234, LS (low) byte of it –C code equivalent: register short x = 0x1234;

29 Direct Memory Addressing This mode accesses the memory directly In the 68HC11: –Direct addressing accesses only locations $0000-$00FF Requires only 8 bits for address (256 locations) CPU automatically sets upper byte of address to $00 Example: LDAA $64 : Loads Register A with Data stored in memory location $0064 –Machine code: $96, $64 –RTL semantics: A ← Mem[$0064] –C code equivalent: register char a = *(0x64); Register A gets set to the contents of address $0064

30 TPS Quizzes

31 Extended Direct Memory Addressing –Extended Direct Memory accesses the entire 64K address space: $ $FFFF This is just called “direct” mode on many other CPUs –Example: LDAA $1234 Loads Register A with data stored in memory location $1234 Requires 16 bits (2 bytes) for the address Machine code: $B6, $12, $34 RTL semantics: A ← Mem[$1234] C code equivalent: register char a = *(0x1234); Register A is loaded with the contents of memory location $1234

32 Register Indexed Addressing Effective address is the sum of an index register (X or Y) and an 8-bit (unsigned) constant offset –This type of addressing is called displacement addressing in many other architectures. Example: LDX #$A13F X  $A13F LDAA $0A,X A  Mem[X+$0A] = Mem[$A149] –Load A with the contents of memory location $A149 –C code equivalent: register char *x, a; Declares variables… x = 0xA13F; Sets up pointer… and then later … a = *(x+10); (also equivalent to a = x[10]; )

33 Register Indirect Addressing Same as Register Index Addressing except we set the offset = 0. Therefore, the effective address comes straight out of the index register Ex: –LDX #$1200 X  $1200 LDAA 0,X A  Mem[0+X] = ($1200) C equivalent: –register char *x, a; x = 0x1200; … a = *x; or a = x[0];

34 Relative Addressing Used implicitly by all branch instructions –Modifies the Program Counter only –8-bit signed value (two’s complement format) Offset ranges $80 to $7F, that is, -128 to +127 This offset gets added to address of the instruction immediately following the branch instruction. –That is, to the “next PC” value after the current instruction has finished being fetched Example: FE infloop: BRA infloop Assembles identically to: FE BRA $1000 More on this later… Note the offset is -2, this gets us from the “next PC” ($1002) back to $1000.

35 CRUCIAL POINT TO REMEMBER! LDAA $64 is using Direct Addressing!! The contents of the A registers are replaced with whatever is the contents of memory location number $0064 Or, shorthand: A  Mem[$64] Unless you are trying to work with the small on-chip RAM (which normally is mapped from $ $01FF), this is probably NOT what you intended to write. LDAA #$64 is using Immediate Addressing The contents of the A register get replaced with the immediate (or constant) value of $64 Or, shorthand: A  $64 This is more often what you will be wanting to do! PLEASE DON’T FORGET THE HASH MARK (#)!

36 TPS Quiz

37 Stack Memory

38 Notation- Stack (Indirect Addressing) Stack Pointer (SP) is a 16 bit address that points to “top” of the Stack Notation –Sp = the value or address stored in the stack pointer register –(Sp) = the contents of the memory location pointed to by Sp.

39 Notation- Stack Example: Let SP=$2000, and $2000: $AA SP = $2000 (SP) = ($2000) = $AA

40 Stack Memory The Stack is a LIFO-Last In First Out Buffer –Stack is stored in RAM –Stack Instructions PSH – Push register data onto Stack –PSHA: (Sp)  A –PSHB: (Sp)  B –PSHX: (Sp)  X –PSHY: (Sp)  Y PUL - Pull register data from Stack –PULA: A <- (Sp) –PULB: B <- (Sp) –PULX: X <- (Sp) –PULY: Y <- (Sp) What’s so special about the stack???

41 Stack Example (8-bit) Push (PSH?) Operation 1.(Sp)  Reg (A or B) 2.SP  SP – 1 Ex: Let A=$23, B=$1D, SP=$2000, ($2000) = $AA Execute: PSHA (SP) = ($2000)=$23, SP=SP-1=$1FFF Execute: PSHB ($1FFF)=$1D, SP=SP-1=$1FFD

42 Stack Example (8-bit) Pull (PUL?) Operation 1.SP  SP Reg (A or B)  (SP) Ex: Let A=$23, B=$1D, SP=$1FFE, ($1FFF) = $AA, ($2000) = $55, ($2001) = $3F Execute: PULA SP=SP+1=$1FFF, A  ($1FFF)=$AA Execute: PULB We have: SP=SP+1=$2000, B  ($2000)=$55

43 Stack Example (16 bit) Push (PSH?) Operation 1.(SP)  Low byte of Reg (X or Y) 2.SP  SP – 1 3.(SP)  High byte of Reg (X or Y) 4.SP  SP – 1 Ex: Let X=$1234, Y=$FEDC, SP=$2000 Execute: PSHX (SP) = ($2000) = $34 (low byte of X) SP  SP-1; (SP)=($1FFF) = $12 (high byte of X) SP  SP – 1 = $1FFE

44 Stack Example (16 bit) Ex: Let X=$1234, Y=$FEDC, SP=$1FFE Execute: PSHY (SP) = ($1FFE) = $DC (low byte of Y) SP  SP-1; (SP)=($1FFD) = $FE (high byte of Y) SP  SP – 1 = $1FFC

45 Stack Example (16-bit) Pull (PUL?) Operation 1.SP  SP High Byte of Reg (X or Y)  (SP) 3.SP  SP Low byte of Reg (X or Y)  (SP) Ex: Let X=$1234, Y=$FEDC, SP=$1FFE, ($1FFF) = $AA, ($2000) = $55, ($2001) = $3F Execute: PULX SP=SP+1=$1FFF, High byte of X (XH)  ($1FFF)= $AA SP  SP+1=$2000, Low byte of X (XL)  ($2000) = $55 So, X  $AA55

46 System ROM System RAM $0000 $FFFF User Program User Data Sample Memory Map User Stack Stack Data RAM

47 Stack Pointer

48 Condition Code Register

49 Condition Code Register Special Register used for control and provide arithmetic information to programmer and CPU. Condition Code Register

50 Condition Code Register S = Stop X = X Interrupt Bit I = Interrupt Mask N = Negative Z = Zero V = Overflow C = Carry H = Half Carry Control Bits Arithmetic Bits

51 Condition Code Register Control Bits set by programmer

52 Condition Code Register S= Stop Disable If set, disables the operation of the STOP instruction. X= X interrupt mask If set, disables the operation of the X interrupt (non-maskable) bit

53 Condition Code Register I= Interrupt mask If set, disables the operation of the interrupt (maskable) bit

54 Interrupts Used to “interrupt” the currently running program to start execution of another program called an –Interrupt Service Routine Types –Hardware Ex: Reset –Software Ex: Illegal Operation

55 Reset Function Hardware Interrupt

56 Reset Action Reset function –Active Low control signal (hardware) –Places controller into a known initial “state.” Stack pointer undefined I and X bits are set – disabling interrupts S bit set to disable STOP instruction Program Vector at location $FFFE:$FFFF is executed.

57 Reset Action Program Vectors –Recall M68HC11 has a 16-bit address space Need two bytes (I.e. word) for one address –Program vector is just a 16 bit address that is loaded into the Program Counter register. Ex: Assume $FFEE = $30 : $FFFF = $00 –When reset is asserted (I.e. reset = 0), the Program Counter register is loaded with – (PC)  $3000 –So that the next instruction will be executed starting at address $3000. This is where we want to have the boot program loaded into ROM.

58 Reset Action Additional actions that occur at Reset –Addresses $0000-$00FF are allocated to RAM –Addresses $1000-$103F are allocated to control registers (later) –Parallel I/O system is configured –Serial I/O system is disabled –A/D system is disabled –Timer system is reset –All registers are indeterminate

59 Condition Code Register Arithmetic Bits Modified by various instructions

60 Condition Code Register N= Negative If set, MSB of the result is one Z= Zero If set, the result is zero

61 Condition Code Register V= Overflow If set, a 2’s complement overflow has occurred C= Carry If set, a carry or borrow out of bit 7 has occurred.

62 Condition Code Register H= Half-Carry If set, there is a carry or borrow out of bit 3

63 TPS Quizzes 10-11

64 End of Section

65 Program Counter