– BlackAn – The Blackfin Analyzer by Jacob Zurasky and Paul Deffenbaugh.

Slides:



Advertisements
Similar presentations
Controller Tests Stephen Kaye Controller Test Motivation Testing the controller before the next generation helps to shake out any remaining.
Advertisements

Computer Architecture
Interface between Velleman PCSGU250 and MATLAB
Basic Raster Graphics Algorithms for Drawing 2D Primitives
Computer Graphics Tz-Huan Huang National Taiwan University (Slides are based on Prof. Chen’s)
PROGRAMMABLE PERIPHERAL INTERFACE -8255
Status – Week 257 Victor Moya. Summary GPU interface. GPU interface. GPU state. GPU state. API/Driver State. API/Driver State. Driver/CPU Proxy. Driver/CPU.
Swish Sleeve Software Design Narrative Team 7: Stephen MacNeil, Michael Kobit, Sriharsh Achukola, Augustus Hong 1Team 7 - Swish Sleeve.
Oscilloscope Watch Teardown. Agenda History and General overview Hardware design: – Block diagram and general overview – Choice of the microcontroller.
Spectrum Analyzer. Another Oscilloscope??? Like an oscilloscope Oscilloscope in time domain Spectrum analyzer in frequency domain (selectable)
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Parallel Programming in C with MPI and OpenMP Michael J. Quinn.
Input-output and Communication Prof. Sin-Min Lee Department of Computer Science.
Computer Software A Lesson Using Concept Attainment EDTE 280 Ben Anderson Diana Ganju Dave Margolis Monica Range Bonnie Sugiyama.
Interrupts (contd..) Multiple I/O devices may be connected to the processor and the memory via a bus. Some or all of these devices may be capable of generating.
Chapter 12 Pipelining Strategies Performance Hazards.
Double buffer SDRAM Memory Controller Presented by: Yael Dresner Andre Steiner Instructed by: Michael Levilov Project Number: D0713.
User-friendly stylus and video surface CAD system Jeremy Schwartz Paul Peeling Faraz Ahmad.
MIT Dance Dance Revolution Anna Ayuso and Sharmeen Browarek *Image source:
Chapter 8: Introduction to High-Level Language Programming Invitation to Computer Science, C++ Version, Fourth Edition.
Input Devices Image Capture Devices, Sound Capture Devices, Remote Controls PREPARED & PRESENTED BY: FAHAD AHMAD KHAN.
Inside The CPU. Buses There are 3 Types of Buses There are 3 Types of Buses Address bus Address bus –between CPU and Main Memory –Carries address of where.
Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz.
DEMONSTRATION FOR SIGMA DATA ACQUISITION MODULES Tempatron Ltd Data Measurements Division Darwin Close Reading RG2 0TB UK T : +44 (0) F :
Bitmapped Images. Bitmap Images Today’s Objectives Identify characteristics of bitmap images Resolution, bit depth, color mode, pixels Determine the most.
The University of New Hampshire InterOperability Laboratory Serial ATA (SATA) Protocol Chapter 10 – Transport Layer.
Lab 2: Capturing and Displaying Digital Image
Piano Dance Revolution - CHARLIE’S ANGELS …and Charlie.
Microcomputer Systems Project By Shriram Kunchanapalli.
GCSE Computing#BristolMet Session Objectives#9 MUST identify the data needed for a computer to display an image correctly (metadata) SHOULD describe the.
7/23 Timers in Coldfire Processor Computer Science & Engineering Department Arizona State University Tempe, AZ Dr. Yann-Hang Lee (480)
 Refers to sampling the gray/color level in the picture at MXN (M number of rows and N number of columns )array of points.  Once points are sampled,
Volume. 1-the idea of the program is to increase, decrease the volume. 2-the program does the following: A-PF8:decrease the volume B-Pf9:increase the.
10/10/04 L5/1/28 COM342 Networks and Data Communications Ian McCrumRoom 5D03B Tel: voice.
AS LEVEL ICT2 Processing Different Types of Information.
EE 445S Real-Time Digital Signal Processing Lab Fall 2013 Lab #2 Generating a Sine Wave Using the Hardware & Software Tools for the TI TMS320C6748 DSP.
Team 6. Code Modules Codec Bluetooth Module Rotary Encoder Menu State Machine.
Introduction to Experiment 5 VGA Signal Generator ECE 448 Spring 2009.
MULTIMEDIA DEFINITION OF MULTIMEDIA
©Brooks/Cole, 2003 Chapter 2 Data Representation.
Lab 8 Bit-Mapped Graphics Moving from text-based graphics to bit- mapped graphics. Easy to draw graphic points and lines using INT 10h, Function 0Ch (write.
Data Logging Solution for Digital Signal Processors Brian Newberry Nekton Research, Inc. James M. Conrad University of North.
MULTIMEDIA INPUT / OUTPUT TECHNOLOGIES
AWB’s Spectrum Analyzer and the Fourier Series waveform reconstruction /12/02 AWB’s Spectrum Analyzer and the Fourier Series waveform reconstruction...
Graphics: Conceptual Model Real Object Human Eye Display Device Graphics System Synthetic Model Synthetic Camera Real Light Synthetic Light Source.
Marwan Al-Namari 1 Digital Representations. Bits and Bytes Devices can only be in one of two states 0 or 1, yes or no, on or off, … Bit: a unit of data.
Chapter 7 Data Sampling Screen Otasuke GP-EX! Chapter 7 Data Sampling Screen.
PPI-8255.
1 Advanced Operating Systems - Fall 2009 Lecture 2 – January 12, 2009 Dan C. Marinescu Office: HEC 439 B.
COMP135/COMP535 Digital Multimedia, 2nd edition Nigel Chapman & Jenny Chapman Chapter 2 Lecture 2 – Digital Representations.
Digital Images and Digital Cameras take notes in your journal.
RTP Usage for CLUE draft-lennox-clue-rtp-usage-02 Clue WG, IETF 83, 27 March 2012 Jonathan Lennox Allyn Romanow
®® Microsoft Windows 7 Windows Tutorial 7 Managing Multimedia Files.
Software Design and Development Storing Data Part 2 Text, sound and video Computing Science.
EE 345S Real-Time Digital Signal Processing Lab Fall 2008 Lab #3 Generating a Sine Wave Using the Hardware & Software Tools for the TI TMS320C6713 DSP.
Real Boxing by Jiaqi Guo. System Flowchart 2 VGA Image Display Module 3 Sprite Graphics.
 Many people like the flexibility of digital images. For example:  They can be shared by attaching to /uploading to Internet  Sent via mobiles.
Image and Sound Representation
Methods of Computer Input and Output
Microprocessor and Assembly Language
TerraForm3D Plasma Works 3D Engine & USGS Terrain Modeler
Lab 5 Part II Instructions
EE 445S Real-Time Digital Signal Processing Lab Fall 2013
Moving Arrays -- 2 Completion of ideas needed for a general and complete program Final concepts needed for Final DMA.
Moving Arrays -- 2 Completion of ideas needed for a general and complete program Final concepts needed for Final DMA.
Lab 2 Part II Instructions
Signal Processing and Data Analysis Simon Godsill Lent 2015
Using Animation and Multimedia
M. Smith Electrical and Computer Engineering University of Calgary,
WJEC GCSE Computer Science
Advanced Computer Architecture Lecture 3
Presentation transcript:

– BlackAn – The Blackfin Analyzer by Jacob Zurasky and Paul Deffenbaugh

Project Goals Display oscilloscope view of audio on TV screen Display oscilloscope view of audio on TV screen Compute and display Fourier Spectrum on TV Compute and display Fourier Spectrum on TV

Tasks Sample Audio Data Sample Audio Data Compute Fourier Spectrum Compute Fourier Spectrum Update Video Memory Update Video Memory Display Video Memory Display Video Memory

Displaying Graphics Memory requirements Memory requirements One Frame = [1716][525] elements One Frame = [1716][525] elements Two frames required to buffer video output Two frames required to buffer video output Active area on TV is 310 x 212 pixels Active area on TV is 310 x 212 pixels

Video Memory SDRAM holds first frame at 0x SDRAM holds first frame at 0x Second frame at 0x000D BF24 Second frame at 0x000D BF24 DMA0 sends data through PPI DMA0 sends data through PPI Video Codec creates the TV signal Video Codec creates the TV signal

SDRAM Problems Writing to SDRAM interrupts reading Writing to SDRAM interrupts reading This causes video glitches This causes video glitches Corrupts the timing of data sent to codec Corrupts the timing of data sent to codec

SDRAM Solution We found that 1-4 pixels can be written We found that 1-4 pixels can be written at the end of each TV line sent This method allows for pixels to This method allows for pixels to be written per frame sent to the TV

SDRAM Solution We changed the DMA0 interrupt to trigger We changed the DMA0 interrupt to trigger on the completion of inner loop (each line) State machine decides what pixels need to be written and blanked at the correct time State machine decides what pixels need to be written and blanked at the correct time

State Machine State 0 – Fill audio buffers State 0 – Fill audio buffers Capture 310 audio samples at 48 kHz Capture 310 audio samples at 48 kHz This is the width of the TV screen This is the width of the TV screen State is changed to 1 upon completion State is changed to 1 upon completion

State Machine State 1 – Process audio data State 1 – Process audio data Compute the DFT if necessary for display Compute the DFT if necessary for display Set to state 2 upon completion Set to state 2 upon completion

State Machine State 2 – Plot data to video memory State 2 – Plot data to video memory At the end of each line sent, draw a new pixel At the end of each line sent, draw a new pixel to the video buffer not being displayed When all current plotting is complete, switch to State 3 When all current plotting is complete, switch to State 3

State Machine State 3 – Swap Video Buffers State 3 – Swap Video Buffers At the end of a complete frame (DMA outer loop), the DMA start address is set to the other video buffer in SDRAM At the end of a complete frame (DMA outer loop), the DMA start address is set to the other video buffer in SDRAM The switch must occur while the DMA is disabled and after completing a frame The switch must occur while the DMA is disabled and after completing a frame

State Machine State 4 – Blank the previous video buffer State 4 – Blank the previous video buffer The buffer not being displayed now must be cleared for new data The buffer not being displayed now must be cleared for new data Write black pixels over the old data Write black pixels over the old data Reset back to State 0 Reset back to State 0

Sampling Audio Data DMA1 uses SPORT0 to receive audio data DMA1 uses SPORT0 to receive audio data DMA2 uses SPORT0 to transmit audio data DMA2 uses SPORT0 to transmit audio data

Sampling Audio Data On interrupt, if State = 0, fill audio buffers On interrupt, if State = 0, fill audio buffers Audio_BufferL[] and Audio_BufferR[] Audio_BufferL[] and Audio_BufferR[] Collect 310 samples of audio Collect 310 samples of audio

Compute the DFT Using this definition, the DFT is computed Using this definition, the DFT is computed

Compute DFT Sine and Cosine factors are pre-computed Sine and Cosine factors are pre-computed This greatly improved the speed of DFT This greatly improved the speed of DFT The lookup tables had to be implemented in SDRAM The lookup tables had to be implemented in SDRAM

Plotting Data to TV There are 4 display modes There are 4 display modes Left channel oscilloscope Left channel oscilloscope Left/Right channel oscilloscope Left/Right channel oscilloscope DFT DFT Left channel oscilloscope and DFT Left channel oscilloscope and DFT

Plotting Data to TV The data is scaled depending on the mode The data is scaled depending on the mode Data is plotted pixel by pixel at the end of each line sent to the TV Data is plotted pixel by pixel at the end of each line sent to the TV Video buffers are swapped once complete Video buffers are swapped once complete

Changing Display Modes Can only occur at the end of a frame Can only occur at the end of a frame Both video buffers must be cleared Both video buffers must be cleared Then change the display mode flag Then change the display mode flag

Future Improvements Add a title screen from a bitmap image Add a title screen from a bitmap image Fine tune the DFT results and scaling Fine tune the DFT results and scaling More display modes More display modes

Questions? Please us at Please us at