NanoFab Simulator Update Nick Reeder, May 17, 2012.

Slides:



Advertisements
Similar presentations
NanoFab Trainer Update Nick Reeder, January 18, 2013.
Advertisements

FABRICATION PROCESSES
CHAPTER 8: THERMAL PROCESS (continued). Diffusion Process The process of materials move from high concentration regions to low concentration regions,
CMOS Process at a Glance
Tutorial 3 Derek Wright Wednesday, February 2 nd, 2005.
Page margin margin for header and footer. page size page orientation.
NanoFab Simulator Update Nick Reeder, May 31, 2012.
Fabrication of p-n junction in Si Silicon wafer [1-0-0] Type: N Dopant: P Resistivity: Ω-cm Thickness: µm.
Ksjp, 7/01 MEMS Design & Fab IC/MEMS Fabrication - Outline Fabrication overview Materials Wafer fabrication The Cycle: Deposition Lithography Etching.
The Physical Structure (NMOS)
Sample Devices for NAIL Thermal Imaging and Nanowire Projects Design and Fabrication Mead Mišić Selim Ünlü.
Quark QuarkXPress 4 Foundation Level Course. What is QuarkXPress? This courseware teaches the fundamentals of QuarkXPress 4.1. It is a page layout application.
The Deposition Process
NanoFab Trainer Update Nick Reeder, April 11, 2014.
NanoFab Trainer Update Nick Reeder, March 14, 2014.
Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-1  10 Micrometer Design Rules  4 Design Layers.
Plasma Etch and the MATEC Plasma Etcher Simulation
Manufacturing Process
NanoFab Simulator Update Nick Reeder, April 20, 2012.
McGill Nanotools Microfabrication Processes
CS/EE 6710 CMOS Processing. N-type Transistor + - i electrons Vds +Vgs S G D.
Fabrication of Active Matrix (STEM) Detectors
NanoFab Trainer Update Nick Reeder, April 5, 2013.
Surface MEMS 2014 Part 1
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #2. Chip Fabrication  Silicon Ingots  Wafers  Chip Fabrication Steps (FEOL, BEOL)  Processing Categories 
Parametric Modeling © 2012 Project Lead The Way, Inc.Introduction to Engineering Design.
SEMINAR ON IC FABRICATION MD.ASLAM ADM NO:05-125,ETC/2008.
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Chapter 2 Manufacturing Process March 7, 2003.
I.C. Technology Processing Course Trinity College Dublin.
II-Lithography Fall 2013 Prof. Marc Madou MSTB 120
ECE484: Digital VLSI Design Fall 2010 Lecture: IC Manufacturing
SEMINAR PRESENTATION ON IC FABRICATION PROCESS
Virtual NanoFab A Silicon NanoFabrication Trainer
NanoFab Simulator Layout Nick Reeder, Dec 16, 2011.
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #3. Diffusion  Introduction  Diffusion Process  Diffusion Mechanisms  Why Diffusion?  Diffusion Technology.
Introduction to Wafer fabrication Process
Top Down Manufacturing
NanoFab Trainer Nick Reeder June 28, 2012.
Introduction EE1411 Manufacturing Process. EE1412 What is a Semiconductor? Low resistivity => “conductor” High resistivity => “insulator” Intermediate.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 3, slide 1 Introduction to Electronic Circuit Design.
NanoFab Trainer Update Nick Reeder, February 28, 2014.
IC Processing. Initial Steps: Forming an active region Si 3 N 4 is etched away using an F-plasma: Si3dN4 + 12F → 3SiF 4 + 2N 2 Or removed in hot.
NanoFab Trainer Update Nick Reeder, March 1, 2013.
Dynamic Behavior of MOS Transistor. The Gate Capacitance t ox n + n + Cross section L Gate oxide x d x d L d Polysilicon gate Top view Gate-bulk overlap.
FULTEC / RPI GaN MESFET Process Flow
Introducing Dreamweaver. Dreamweaver The web development application used to create web pages Part of the Adobe creative suite.
NanoFab Trainer Update Nick Reeder, April 25, 2014.
Plasma bay modernised in Sentech SI 500 RIE cluster Si 3 N 4, SiO 2, polySi and Al etching 2 x Oxford System 100 ICP Si 3 N 4, SiO 2, polySi, polymers,
Fab - Step 1 Take SOI Wafer Top view Side view Si substrate SiO2 – 2 um Si confidential.
Side ViewTop View Beginning from a silicon wafer.
EE141 Manufacturing 1 Chapter 2 Manufacturing Process and CMOS Circuit Layout 1 st rev. : March 7, nd rev. : April 10, 2003.
Sputtering. Why? Thin layer deposition How? Bombarding a surface with ions which knocks out molecules from a target which in turn will redeposit onto.
(Chapters 29 & 30; good to refresh 20 & 21, too)
1 Device Fabrication And Diffusion Overview 5 and 8 February 2016 Silicon Wafer Production-Refer to Chapter “0” Prologue Raw material ― Polysilicon nuggets.
MOSCAP Characterization of SNF ALD
Lecture 2 State-of-the art of CMOS Technology
Solar Cell and NMOS Transistor Process EE290G Joey Greenspun.
IC Manufactured Done by: Engineer Ahmad Haitham.
Basic Planar Processes
Microfabrication Home 3 exercise Return by Feb 5th, 22 o’clock
Microfabrication Home exercise 1
1) Wafer Cleaning Oxidizing – Field Oxide
Fab. Example: Piezoelectric Force Sensor (1)
NanoFab Simulator Update
VLSI System Design LEC3.1 CMOS FABRICATION REVIEW
Digital Integrated Circuits A Design Perspective
Silicon Wafer cm (5’’- 8’’) mm
Chapter 1.
NanoFab Trainer Update
Presentation transcript:

NanoFab Simulator Update Nick Reeder, May 17, 2012

Minor Updates Thermal Oxidize code: No longer identifies SiO2 as doped after doped Si is oxidized. Added ion mill, CF4, and SF6 plasma etches. – Had to make many assumptions, due to scarcity of data in Williams’ etch-rate tables. Changed vertical and horizontal scales on display. – Question: What should height and width of displayed area be (in microns), and does this need to be adjustable by the user?

Updates to Implant Code User now specifies dopant, dose, and ion energy. Code computes depth and doping concentration. Thresholds for doping levels: – Undoped if concentration < ions/cm 3 – n or p if  concentration < – n+ or p+ if  concentration < – n++ or p++ if  concentration

Updates to Sputter Code User now specifies sputtering angle, and code simulates deposition from that angle. Fixed: sputter is no longer deposited on shaded surfaces. Algorithm is iterative and time-consuming due to complexity of resulting contours.

To-Do List Write new code for – Bake – Lift-off – Clean – Profilometer Fix spin-coat code so that resist does not adhere to underside of horizontal surfaces. In expose code, implement diffraction of UV in air and absorption within resist. Add other dry etchants (listed in 3/30/12 meeting). Fix evaporate, CVD, sputter, oxidize, develop, polish dialog boxes to ask user for correct parameters, and write code to compute depth from these values. Write time-cost-quality code for all operations. Write online help text. Produce videos, photos, text for “Learning” tab.

ActivityNot startedPartialComplete Simulation coding CleanX Spin coatX BakeX Mask/Expose/DevelopX EvaporateX Thermal oxidationX CVDX SputterX Wet etchX Plasma etchX Lift offX PolishX ImplantX Track time, cost, quality of each processX User -interface coding History with option to revertX Save/open history filesX Edit colorsX User-defined materialsX ProfilometerX Producing embedded media (videos, photos, etc.)X TestingX DocumentationX