Addressing Future HPC Demand with Multi-core Processors Stephen S. Pawlowski Intel Senior Fellow GM, Architecture and Planning CTO, Digital Enterprise Group September 5, 2007

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3 Intel Is Listening… With multi-core processors, however, we finally get to a scheme where the HEP execution profile shines. Thanks to the fact that our jobs are embarrassingly parallel (each physics event is independent of the others) we can launch as many processes (or jobs) as there are cores on a die. However, this requires that the memory size is increased to accommodate the extra processes (making the computers more expensive). As long as the memory traffic does not become a bottleneck, we see a practically linear increase in the throughput on such a system. A ROOT/PROOF analysis demo elegantly demonstrated this during the launch of the quad- core chip at CERN. Source: “ Processors size up for physics at the LHC” Sverre Jarp,CERN Courier, March 28, 2007 Sverre Jarp, CERN Courier, March 28, 2007 HEP – High Energy Physics LHC - Large Hadron Collider

4 Accelerating Multi- and Many-core Performance Through Parallelism Power delivery and management High bandwidth memory Reconfigurable cache Scalable fabric Fixed-function units Big Core Core Big Core Big cores for Single Thread PerformanceBig cores for Single Thread Performance Small cores for Multi-Thread PerformanceSmall cores for Multi-Thread Performance

5 Memory Bandwidth Demand Computational Fluid Dynamic (CFD) - Splash Memory Bandwidth (GB/Sec) Computation (GFlops) x50x50, 10fps 150x100x100, 10fps 75x50x50, 30fps 150x100x100, 30fps 5000 Source: Intel Labs TFLOP Or 1 TB/s 0.17 Byte/Flop DDR3 Bandwidth (GB/Sec) Assuming frequency: 2133MHz ,4,8,16,32,64 DDR3 channels

6 Increasing Signaling Rate More Bandwidth & Less Power Differential Copper Interconnect & Silicon Photonics Signaling Rate MHz Power (mW/Gbps) State of the art DDR Single-ended Interconnect Future State of the Art with FBD & 5Gb/s): 100 GB/sec ~ 1 Tb/sec = 1,000 Gb/sec  25mw/Gb/sec = 25 Watts Bus-width = 1,000 Gb/sec / 5 = 200, about 400 pins (differential) Signaling Rate GBit/sec Power (mW/Gbps) State of the art with FBD Future Copper Interconnect Optical today 40 Silicon Photonics Vision 40

7 Addressing Memory Bandwidth Bringing Memory Closer to the Cores Package DRAMCPU Heat-sink Last Level Cache Fast DRAM Memory on Package *Future Vision, does not represent real Intel product 3D Memory Stacking Package Si Chip

8 Photonics For Memory BW and Capacity High Performance with Remote Memory Rx Tx The Indium Phosphide emits the light into the silicon waveguide The silicon acts as laser cavity - Light bounces back and forth and get amplified by InP based material integrated silicon photonic chip Remote Memory Blade integrated into a system Integrated Tb/s Optical Link on a Single Chip

9 Increasing Ethernet Bandwidth TPC-H SPECweb05 TPC-C SPECjApps 10 Gb/s 20Gb/s SPECweb05 TPC-H 40Gb/s 30Gb/s 50Gb/s 60Gb/s 70Gb/s 80Gb/s SPECweb05 TPC-H TPC-C TPC-H Source: Intel, TPC & SPEC are standard server application benchmarks Today server I/O is fragmented 1GbE performance doesn’t meet current server I/O requirements 10GbE is still too expensive 2/4G Fibre Channel & 10G Infiniband are being deployed to meet the growing I/O demands for storage & HPC clusters In 2-4 Years, convergence on 10GbE looks promising 10GBASE-T availability will drive costs down 10GbE will offer a compelling value- proposition for LAN, SAN, & HPC cluster connections 7-10 Years Look beyond to 40GbE and 100GbE ~2x Perf Gain Every 2 Years

10 Outside the Box: HPC Networking with Optical Cables Benefit Over Copper: Scalable, BW, throughput Scalable, BW, throughput Longer distance – today up to 100m Longer distance – today up to 100m Higher reliability: 10ˉ 15 Bit Error Rate (BER) or lower Higher reliability: 10ˉ 15 Bit Error Rate (BER) or lower Smaller & lighter form factor Smaller & lighter form factor Electrical Socket Optical Transceiver in Plug Optical Cable Optical Transceiver in Plug Up to 100m Electrical Socket Gb/s 40Gb/s 100Gb/s 80Gb/s 120Gb/s Doubling the Data Rate Every 2 Years

11 Power Aware Everywhere Silicon Heat Sinks Systems Facilities Packages Silicon: Moore’s law, Strained silicon, Transistor leakage control techniques, Hi-K Dielectric, Clock gating, etc. Processor and System Power: Multi-core, Integrated Voltage Regulators (IVR), Fine grain power management, etc. Facilities: Efficient Power Conversion and Cooling

12 Reliability Challenges & Vision Source: Intel + V + V Depletion Region Drift Diffusion Ion Path An exponential growth in FIT/chip FIT/bit of memory cell: expected to be roughly constant, but,FIT/bit of memory cell: expected to be roughly constant, but, Moore’s law: increasing the bit count exponentially: 2x every 2 yearsMoore’s law: increasing the bit count exponentially: 2x every 2 years Source: Intel Soft Error: one of many reliability challenges Process Techniques Device Param Tuning Rad-hard Cell Creation Circuit Techniques Architectural Techniques Micro Solutions Macro Solutions Parity SECDED ECC π bit Lockstepping Redundant multithreading (RMT) Redundant multi-core CPU State-of-Art Processes

13 What Can We Expect?! 10 PFlops 1 PFlops 100 TFlops 10 TFlops 1 TFlops 100 GFlops 10 GFlops 1 GFlops 100 MFlops 100 PFlops 10 EFlops 1 EFlops 100 EFlops HPC 1 ZFlops # Background picture from CERN OpenLab, Intel HPC Roundtable ‘06 SUM Of Top500 Beyond Petascale CERN: 115th of Top500 in June 2007 source: CERN Courier, Aug. 20, 2007

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